7-958

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4063BMS

CMOS 4-Bit Magnitude Comparator

Pinout

CD4063BMS

TOP VIEW

Functional Diagram

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

B3

(A < B) IN

(A = B) IN

(A > B) IN

(A > B) OUT

(A = B) OUT

VSS

(A < B) OUT

VDD

B2

A2

A1

B1

A0

B0

A3

A > B

A = B

A < B

A > B

A = B

A < B

CASCADING

INPUTS

WORD A

4

WORD B

4

Features

• High Voltage Type (20V Rating)

• Expansion to 8, 12, 16 . . . 4N Bits by Cascading Units

• Medium Speed Operation

- Compares Two 4-Bit Words in 250ns (Typ.) at 10V

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1

µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25oC

• Noise Margin (Full Package Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Servo Motor Controls

• Process Controllers

Description

CD4063BMS is a 4-bit magnitude comparator designed for use

in computer and logic applications that require the comparison of

two 4-bit words. This logic circuit determines whether one 4-bit

word (Binary or BCD) is “less than”, “equal to”, or “greater than” a

second 4-bit word.

The CD4063BMS has eight comparing inputs (A3, B3, through

A0, B0), three outputs (A < B, A = B, A > B) and three cascading

inputs (A < B, A = B, A > B) that permit systems designers to

expand the comparator function to 8, 12, 16 . . . 4N bits. When a

single CD4063BMS is used, the cascading inputs are connected

as follows: (A < B) = low, (A = B) = high, (A > B) = low.

For words longer than 4 bits, CD4063BMS devices may be cas-

caded by connecting the outputs of the less significant compara-

tor to the corresponding cascading inputs of the more significant

comparator. Cascading inputs (A < B, A = B, and A > B) on the

least significant comparator are connected to a low, a high, and a

low level, respectively.

The CD4063BMS is supplied in these 16 lead outline pack-

ages:

Braze Seal DIP

H4T

Frit Seal DIP

H1E

Ceramic Flatpack

H6W

December 1992

File Number

3318