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IDTCSPT855

2.5V PLL CLOCK DRIVER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

200

8 Integrated Device Technology, Inc.

DSC-6203/1

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c

IDTCSPT855

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2.5V PHASE LOCKED LOOP

CLOCK DRIVER

PLL

CLK

CLK

6

7

23

22

FBIN

FBIN

PWRDWN

24

9

AVDD

POWERDOWN

AND TEST

LOGIC

Y0

Y0

Y1

Y1

12

13

FBOUT

FBOUT

19

20

Y3

Y3

26

27

Y2

Y2

17

16

3

2

NOVEMBER

2008

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• PLL clock driver for DDR (Double Data Rate) synchronous

DRAM applications

• Spread spectrum clock compatible

• Operating frequency: 60MHz to 220MHz

• Low jitter (cycle-to-cycle): ±50ps

• Distributes one differential clock input to four differential clock

outputs

• Enters low power mode and 3-state outputs when input CLK

signal is less than 20MHz or PWRDWN is low

• Operates from a 2.5V supply

• Consumes <200

μμμμμA quiescent current

• External feedback pins (FBIN,

FBIN) are used to synchronize

outputs to input clocks

• Available in TSSOP package

DESCRIPTION:

The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer

that distributes one differential clock input pair(CLK,

CLK ) to four differential

output pairs (Y[0:3], Y [0:3]) and one differential pair of feedback clock outputs

(FBOUT,

FBOUT). WhenPWRDWNishigh,theoutputsswitchinphaseand

frequencywithCLK. When

PWRDWNislow,alloutputsaredisabledtoahigh-

impedance state (3-state), and the PLL is shut down (low-power mode). The

device also enters this low-power mode when the input frequency falls below

asuggesteddetectionfrequencythatisbelow20MHz(typical10MHz). Aninput

frequency detection circuit detects the low-frequency condition, and after

applying a >20MHz input signal, this detection circuit reactivates the PLL and

enables the outputs.

When AVDD is tied to GND, the PLL is turned off and bypassed for test

purposes. The CSPT855 is also able to track spread spectrum clocking for

reduced EMI.

Since the CSPT855 is based on PLL circuitry, it requires a stabilization time

to achieve phase-lock of the PLL. This stabilization time is required following

power up.

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS:

• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),

PC2700 (DDR333), PC3200 (DDR400)