AX88871AP datasheet(9/30 Pages) ASIX

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AX88871AP Bripeater

ASIX ELECTRONICS CORPORATION

2.0 Pin Description

The following terms describe the AX88871A pinout:

All pin names with the “/” suffix are asserted low.

Input

Output

I/O

Input /Output

2.1 MII interfaces

Signal Name

Type

Pin No.

Description

TXER[7:0]

COL[7:0]

89, 72, 56

40, 24, 9

202, 187

Transmit Error : When /HALF10 pin set to “high”. TXER is transition

synchronously with respect to the rising edge of TXCLK . Asserted

high when a code violation is request to be send

Collision : When /HALF10 pin set to “low”. COL is input from PHY,

when 10Mbps PHY is in half-duplex mode.

TXD[7:0][3:0]

88-85, 70-67

55-52, 39-36

23-20, 8-5

201-198

186-185

182-181

Transmit Data : TXD[3:0] is transition synchronously with respect to

the rising edge of TXCLK. For each TXCLK period in which TXEN is

asserted, TXD[3:0] are accepted for transmission by the PHY.

TXEN[7:0]

84, 66,51

35, 19, 4

197, 180

Transmit Enable : TXEN is transition synchronously with respect to the

rising edge of TXCLK. TXEN indicates that the port is presenting

nibbles on TXD [3:0] for transmission.

RXD[7:0][3:0]

83-80, 65-62

49-46, 34-31

18-15, 3-2

208-207

195-192

179-176

Receive Data : RXD [3:0] is driven by the PHY synchronously with

respect to RXCLK.

RXER[7:0]

74, 57, 42

27, 11, 203,

188, 172

Receive Error : RXER ,is driven by PHY and synchronous to RXCLK,

is asserted for one or more RXCLK periods to indicate to the port that

an error has detected.

RXCLK[7:0]

79, 61, 45

30, 14, 206,

191, 175

Receive Clock : RX_CLK is a continuous clock that provides the

timing reference for the transfer of the RXDV,RXD [3:0] and RXER

signals from the PHY to the MII port of the repeater.

RXDV[7:0]

75, 58, 43

28, 12, 204,

189, 173

Receive Data Valid : RX_DV is driven by the PHY synchronously with

respect to RXCLK. Asserted high when valid data is present on RXD

[3:0].

CRS[7:0]

76, 59, 44, 29,

13, 205, 190,

174

Carrier Sense : Asynchronous signal CRS is asserted by the PHY when

receive medium is non-idle at full duplex mode.

COL_O[6]

Collision : Collision detection signal for port 6

COL_O[7]

Collision : Collision detection signal for port 7

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