6.42

71321SA/LA and 71421SA/LA

High Speed 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

13

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform of BUSY Arbitration Controlled

by Address Match Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. IftAPSisnotsatisfied,theBUSYwillbeassertedononesideortheother,butthereisnoguaranteeonwhichsideBUSYwillbeasserted(IDT71321only).

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

NOTE:

1. 'X' in part numbers indicates power rating (SA or LA).

tAPS

(2)

ADDR "A"

AND "B"

ADDRESSES MATCH

tBAC

tBDC

CE"B"

CE"A"

BUSY"A"

2691 drw 12

BUSY"B"

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

tAPS

(2)

ADDR"A"

ADDR"B"

2691 drw 13

tBAA

tBDA

tRC or tWC

71321X20

71421X20

Com'l Only

71321X25

71421X25

Com'l

& Ind

Symbol

Parameter

Min.Max.Min.Max.

Unit

INTERRUPT TIMING

tAS

Address Set-up Time

0

____

0

____

ns

tWR

Write Recovery Time

0

____

0

____

ns

tINS

Interrupt Set Time

____

20

____

25

ns

tINR

Interrupt Reset Time

____

20

____

25

ns

2691 tbl 11a