Philips Semiconductors

Product specification

83C576/87C576

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

1998 Jun 04

21

÷2

÷2

÷2

÷2

÷2

÷2

÷2

PRE2

PRE1

PRE0

000

001

010

011

100

101

110

111

OSC/2

÷64

÷64

÷128

÷256

÷512

÷1024

÷2048

÷4096

÷8192

TO WATCHDOG

DOWN COUNTER

DECODE

SU00660

Figure 18.

Watchdog Prescaler

SCON Address = 98H

Reset Value = 0000 0000B

SM0/FE

SM1

SM2

REN

TB8

RB8

Tl

Rl

Bit Addressable

(SMOD0/1)*

Symbol

Function

FE

Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

SM1

Serial Port Mode Bit 1

SM0

SM1

Mode

Description

Baud Rate**

0

0

0

shift register

0

1

1

8-bit UART

variable

1

0

2

9-bit UART

1

1

3

9-bit UART

variable

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.

In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a

Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

RB8

In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0/1 is located at PCON.6, PCON.7

SU00766

Bit:

7654

321

0

Figure 19.

SCON: Serial Port Control Register