PES10T4G2 datasheet(2/31 Pages) RENESAS

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May 10, 2016

IDT 89HPES10T4G2 Data Sheet

• Power Management

— Utilizes advanced low-power design techniques to achieve

low typical power consumption

— Support PCI Express Power Management Interface specifica-

tion (PCI-PM 1.2)

— Supports PCI Express Active State Power Management

(ASPM) link state

— Supports PCI Express Power Budgeting Capability

— Supports the optional PCI Express SerDes Transmit Low-

Swing Voltage Mode

— Unused SerDes are disabled and can be powered-off.

• Testability and Debug Features

— Built in Pseudo-Random Bit Stream (PRBS) generator

— Numerous SerDes test modes

— Ability to read and write any internal register via the SMBus

— Ability to bypass link training and force any link into any mode

— Provides statistics and performance counters

• Nine General Purpose Input/Output Pins

— Each pin may be individually configured as an input or output

— Each pin may be individually configured as an interrupt input

— Some pins have selectable alternate functions

• Packaged in a 19mm x 19mm 324-ball BGA with 1mm ball

spacing

Product Description

Utilizing standard PCI Express interconnect, the PES10T4G2

provides the most efficient fan-out solution for applications requiring high

throughput, low latency, and simple board layout with a minimum

number of board layers. It provides 12 GBps (96 Gbps) of aggregated,

full-duplex switching capacity through 10 integrated serial lanes, using

proven and robust IDT technology. Each lane provides 5 Gbps of band-

width in both directions and is fully compliant with PCI Express Base

Specification, Revision 2.0.

The PES10T4G2 is based on a flexible and efficient layered architec-

ture. The PCI Express layer consists of SerDes, Physical, Data Link and

Transaction layers in compliance with PCI Express Base specification

Revision 2.0. The PES10T4G2 can operate either as a store and

forward or cut-through switch and is designed to switch memory and I/O

transactions. It supports eight Traffic Classes (TCs) and one Virtual

Channel (VC) with sophisticated resource management to enable effi-

cient switching and I/O connectivity for servers, storage, and embedded

processors with limited connectivity.

Figure 2 I/O Expansion Application

SMBus Interface

The PES10T4G2 contains two SMBus interfaces. The slave inter-

face provides full access to the configuration registers in the

PES10T4G2, allowing every configuration register in the device to be

read or written by an external agent. The master interface allows the

default configuration register values of the PES10T4G2 to be over-

ridden following a reset with values programmed in an external serial

EEPROM. The master interface is also used by an external Hot-Plug I/O

expander.

Six pins make up each of the two SMBus interfaces. These pins

consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus

address pins. In the slave interface, these address pins allow the

SMBus address to which the device responds to be configured. In the

master interface, these address pins allow the SMBus address of the

serial configuration EEPROM from which data is loaded to be config-

ured. The SMBus address is set up on negation of PERSTN by

sampling the corresponding address pins. When the pins are sampled,

the resulting address is assigned as shown in Table 1.

Bit

Slave

SMBus

Address

Master

SMBus

Address

SSMBADDR[1]

MSMBADDR[1]

SSMBADDR[2]

MSMBADDR[2]

SSMBADDR[3]

MSMBADDR[3]

MSMBADDR[4]

SSMBADDR[5]

Table 1 Master and Slave SMBus Address Assignment

Memory

Processor

Memory

North

Bridge

PES10T4G2

I/O

10GbE

I/O

10GbE

I/O

SATA

PCI Express

Slot

Processor

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