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SC87C51CYA44 Datasheet(PDF) 16 Page - NXP Semiconductors |
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SC87C51CYA44 Datasheet(HTML) 16 Page - NXP Semiconductors |
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16 / 30 page  Philips Semiconductors Product specification 80C31/80C51/87C51 CMOS single-chip 8-bit microcontrollers 1996 Aug 16 16 AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK VARIABLE CLOCK4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1/tCLCL 1 Oscillator frequency Speed versions : P (24MHz) : Y (33MHz) 3.5 24 3.5 33 3.5 33 MHz tLHLL 1 ALE pulse width 43 2tCLCL–40 21 ns tAVLL 1 Address valid to ALE low 17 tCLCL–25 5 ns tLLAX 1 Address hold after ALE low 17 tCLCL–25 ns tLLIV 1 ALE low to valid instruction in 102 4tCLCL–65 55 ns tLLPL 1 ALE low to PSEN low 17 tCLCL–25 5 ns tPLPH 1 PSEN pulse width 80 3tCLCL–45 45 ns tPLIV 1 PSEN low to valid instruction in 65 3tCLCL–60 30 ns tPXIX 1 Input instruction hold after PSEN 0 0 0 ns tPXIZ 1 Input instruction float after PSEN 17 tCLCL–25 5 ns tAVIV 1 Address to valid instruction in 128 5tCLCL–80 70 ns tPLAZ 1 PSEN low to address float 10 10 10 ns Data Memory tRLRH 2, 3 RD pulse width 150 6tCLCL–100 82 ns tWLWH 2, 3 WR pulse width 150 6tCLCL–100 82 ns tRLDV 2, 3 RD low to valid data in 118 5tCLCL–90 60 ns tRHDX 2, 3 Data hold after RD 0 0 0 ns tRHDZ 2, 3 Data float after RD 55 2tCLCL–28 32 ns tLLDV 2, 3 ALE low to valid data in 183 8tCLCL–150 90 ns tAVDV 2, 3 Address to valid data in 210 9tCLCL–165 105 ns tLLWL 2, 3 ALE low to RD or WR low 75 175 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 2, 3 Address valid to WR low or RD low 92 4tCLCL–75 45 ns tQVWX 2, 3 Data valid to WR transition 12 tCLCL–30 0 ns tWHQX 2, 3 Data hold after WR 17 tCLCL–25 5 ns tQVWH 3 Data valid to WR high 162 7tCLCL–130 80 ns tRLAZ 2, 3 RD low to address float 0 0 0 ns tWHLH 2, 3 RD or WR high to ALE high 17 67 tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 5 High time 17 17 tCLCL–tCLCX ns tCLCX 5 Low time 17 17 tCLCL–tCHCX ns tCLCH 5 Rise time 5 5 ns tCHCL 5 Fall time 5 5 ns Shift Register tXLXL 4 Serial port clock cycle time 505 12tCLCL 360 ns tQVXH 4 Output data setup to clock rising edge 283 10tCLCL–133 167 ns tXHQX 4 Output data hold after clock rising edge 3 2tCLCL–80 ns tXHDX 4 Input data hold after clock rising edge 0 0 0 ns tXHDV 4 Clock rising edge to input data valid 283 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 15. |
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