Low Skew, 1-to-2 Differential-to-LVDS

Fanout Buffer

85411I

Data Sheet

©2016 Integrated Device Technology, Inc

Revision B January 20, 2016

1

GENERAL DESCRIPTION

The 85411I is a low skew, high performance 1-to-2 Differential-

to-LVDS Fanout Buffer and a member of the family of High

Performance Clock Solutions from IDT. The CLK, nCLK pair

can accept most standard differential input levels.The 85411I is

characterized to operate from a 3.3V power supply. Guaranteed

output and part-to-part skew characteristics make the 85411I ideal

for those clock distribution applications demanding well defined

performance and repeatability.

FEATURES

• Two differential LVDS outputs

• One differential CLK, nCLK clock input

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 650MHz

• Translates any single ended input signal to

LVDS levels with resistor bias on nCLK input

• Output skew: 25ps (maximum)

• Part-to-part skew: 300ps (maximum)

• Additive phase jitter, RMS: 0.05ps (typical)

• Propagation delay: 2.5ns (maximum)

• 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead free (RoHS 6) package

BLOCK DIAGRAM

PIN ASSIGNMENT

85411I

8-Lead SOIC

3.90mm x 4.90mm x 1.37mm package body

M Package

Top View

Q0

nQ0

Q1

nQ1

1

2

3

4

VDD

CLK

nCLK

GND

8

7

6

5

Q0

nQ0

Q1

nQ1

CLK

nCLK