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89C536 Datasheet(PDF) 18 Page - NXP Semiconductors |
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89C536 Datasheet(HTML) 18 Page - NXP Semiconductors |
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18 / 35 page  Philips Semiconductors Preliminary specification 89C535/89C536/89C538 CMOS single-chip 8-bit microcontrollers with FLASH program memory 1997 Jun 05 18 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 9 Oscillator frequency Speed versions : N (33MHz) 3.5 33 3.5 33 MHz tLHLL 9 ALE pulse width 2tCLCL–40 21 ns tAVLL 9 Address valid to ALE low tCLCL–25 5 ns tLLAX 9 Address hold after ALE low tCLCL–25 5 ns tLLIV 9 ALE low to valid instruction in 4tCLCL–65 55 ns tLLPL 9 ALE low to PSEN low tCLCL–25 5 ns tPLPH 9 PSEN pulse width 3tCLCL–45 45 ns tPLIV 9 PSEN low to valid instruction in 3tCLCL–60 30 ns tPXIX 9 Input instruction hold after PSEN 0 0 ns tPXIZ 9 Input instruction float after PSEN tCLCL–25 5 ns tAVIV 9 Address to valid instruction in 5tCLCL–80 70 ns tPLAZ 9 PSEN low to address float 10 10 ns Data Memory tRLRH 10, 11 RD pulse width 6tCLCL–100 82 ns tWLWH 10, 11 WR pulse width 6tCLCL–100 82 ns tRLDV 10, 11 RD low to valid data in 5tCLCL–90 60 ns tRHDX 10, 11 Data hold after RD 0 0 ns tRHDZ 10, 11 Data float after RD 2tCLCL–28 32 ns tLLDV 10, 11 ALE low to valid data in 8tCLCL–150 90 ns tAVDV 10, 11 Address to valid data in 9tCLCL–165 105 ns tLLWL 10, 11 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 10, 11 Address valid to WR low or RD low 4tCLCL–75 45 ns tQVWX 10, 11 Data valid to WR transition tCLCL–30 0 ns tWHQX 10, 11 Data hold after WR tCLCL–25 5 ns tQVWH 11 Data valid to WR high 7tCLCL–130 80 ns tRLAZ 10, 11 RD low to address float 0 0 ns tWHLH 10, 11 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 13 High time 17 tCLCL–tCLCX ns tCLCX 13 Low time 17 tCLCL–tCHCX ns tCLCH 13 Rise time 5 ns tCHCL 13 Fall time 5 ns Shift Register tXLXL 12 Serial port clock cycle time 12tCLCL 360 ns tQVXH 12 Output data setup to clock rising edge 10tCLCL–133 167 ns tXHQX 12 Output data hold after clock rising edge 2tCLCL–80 50 ns tXHDX 12 Input data hold after clock rising edge 0 0 ns tXHDV 12 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. |
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