MPC9315

MOTOROLA

TIMING SOLUTIONS

2

Figure 1. MPC9315 Logic Diagram

GND

QA1

QA0

VCC

FSELC

FSELB

FSELA

VCC

QC0

QC1

GND

VCC

PSELA

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12

345678

24

23

22

21

20

19

18

17

16

MPC9315

OE

Figure 2. Pinout: 32–Lead Package Pinout (Top View)

GND

Bank A

PLL

(pulldown)

FB_SEL

QA0

QA1

REF_SEL

CLK0

0

1

CLK1

Ref

FB

75 - 160 MHz

CLK

CLK

÷ 2

CLK

÷ 4

QC1

QB0

0

1

0

1

Bank B

Bank C

FSELA

FSELC

VCCA

VCC

6

(pulldown)

(pulldown)

FB0

0

1

FB1

(pulldown)

(pulldown)

(pulldown)

(pulldown)

QB2

QB3

QC0

QB1

FSELB

(pulldown)

(pullup)

(pullup)

OE

GND

6

0

1

PSELA

(pulldown)

0

1

FBSEL

The MPC9315 requires an external RC filter for the analog power supply pin VCCA. Please see application section for details.