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AD7940 Datasheet(PDF) 18 Page - Analog Devices |
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AD7940 Datasheet(HTML) 18 Page - Analog Devices |
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18 / 24 page ![]() AD7693 Preliminary Technical Data Rev. PrB | Page 18 of 24 CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7693 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 35, and the corresponding timing is given in Figure 36. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7693 then enters the acquisition phase and powers down. The data bits are clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge will allow a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. If multiple AD7693s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. DATA IN IRQ CLK CONVERT VIO DIGITAL HOST CNV SCK SDO SDI VIO AD7693 CS Figure 35. 3-Wire Mode with Busy Indicator Connection Diagram (SDI High) SDO D15 D14 D1 D0 tDIS SCK 1 2 3 15 16 17 tSCK tSCKL tSCKH tHSDO tDSDO CNV CONVERSION ACQUISITION tCONV tCYC ACQUISITION SDI = 1 tCNVH tACQ CS Figure 36. 3-Wire Mode with Busy Indicator Serial Interface Timing (SDI High) |
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