HA5022

FN3392 Rev.7.00

Page 7 of 16

May 2003

Application Information

Optimum Feedback Resistor

The plots of inverting and non-inverting frequency response,

see Figure 11 and Figure 12 in the Typical Performance

Curves section, illustrate the performance of the HA5022 in

various closed loop gain configurations. Although the

bandwidth dependency on closed loop gain isn’t as severe as

that of a voltage feedback amplifier, there can be an

appreciable decrease in bandwidth at higher gains. This

decrease may be minimized by taking advantage of the current

feedback amplifier’s unique relationship between bandwidth

and RF . All current feedback amplifiers require a feedback

resistor, even for unity gain applications, and RF, in

conjunction with the internal compensation capacitor, sets the

dominant pole of the frequency response. Thus, the amplifier’s

bandwidth is inversely proportional to RF. The HA5022 design

is optimized for a 1000

 RF at a gain of +1. Decreasing RF in a

unity gain application decreases stability, resulting in

excessive peaking and overshoot. At higher gains the amplifier

is more stable, so RF can be decreased in a trade-off of

stability for bandwidth.

The table below lists recommended RF values for various

gains, and the expected bandwidth.

PC Board Layout

The frequency response of this amplifier depends greatly on

the amount of care taken in designing the PC board. The use

of low inductance components such as chip resistors and chip

capacitors is strongly recommended. If leaded components are

used the leads must be kept short especially for the power

supply decoupling components and those components

connected to the inverting input.

Attention must be given to decoupling the power supplies. A

large value (10

F) tantalum or electrolytic capacitor in parallel

with a small value (0.1

F) chip capacitor works well in most

cases.

A ground plane is strongly recommended to control noise.

Care must also be taken to minimize the capacitance to ground

seen by the amplifier’s inverting input (-IN). The larger this

capacitance, the worse the gain peaking, resulting in pulse

overshoot and possible instability. It is recommended that the

ground plane be removed under traces connected to -IN, and

that connections to -IN be kept as short as possible to

minimize the capacitance from this node to ground.

Driving Capacitive Loads

Capacitive loads will degrade the amplifier’s phase margin

resulting in frequency response peaking and possible

oscillations. In most cases the oscillation can be avoided by

placing an isolation resistor (R) in series with the output as

shown in Figure 6.

The selection criteria for the isolation resistor is highly

dependent on the load, but 27

 has been determined to be a

good starting value.

Power Dissipation Considerations

Due to the high supply current inherent in dual amplifiers, care

must be taken to insure that the maximum junction

temperature (TJ, see Absolute Maximum Ratings) is not

exceeded. Figure 7 shows the maximum ambient temperature

versus supply voltage for the available package styles (PDIP,

SOIC). At VS = 5V quiescent operation both package styles

may be operated over the full industrial range of -40oC to

85oC. It is recommended that thermal calculations, which take

into account output power, be performed by the designer.

Enable/Disable Function

When enabled the amplifier functions as a normal current

feedback amplifier with all of the data in the electrical

specifications table being valid and applicable. When disabled

GAIN

(ACL)RF ()

BANDWIDTH

(MHz)

-1

750

100

+1

1000

125

+2

681

95

+5

1000

52

+10

383

65

-10

750

22

VIN

VOUT

CL

RT

+-

RI

RF

R

FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION

RESISTOR, R

100



140

130

120

110

100

90

80

57

9

11

13

15

SUPPLY VOLTAGE (

V)

PDIP

SOIC

FIGURE 7. MAXIMUM OPERATING AMBIENT

TEMPERATURE vs SUPPLY VOLTAGE