ICS840272I DATA SHEET

SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR

10

REVISION A 06/19/14

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both signals must meet the VPP and VCMR

input requirements. Figure 3A to Figure 3F show interface examples

for the CLK/nCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. Please consult

with the vendor of the driver component to confirm the driver

termination requirements. For example, in Figure 3A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

Figure 3A. CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 3B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3C. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 3D. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3E. CLK/nCLK Input Driven by a

3.3V LVDS Driver

Figure 3F. CLK/nCLK Input Driven by a

2.5V SSTL Driver

R1

50

Ω

R2

50

Ω

Zo = 50

Ω

CLK

nCLK

LVHSTL

IDT

LVHSTL Driver

Differential

Input

R3

3.3K

Ω

1.8V

1.8V

Zo = 50

Ω

3.3V

3.3V

CLK

nCLK

3.3V

3.3V

LVPECL

Differential

Input

127

Ω

120

Ω

82.5

Ω

82.5

Ω

HCSL

*R3

*R4

CLK

nCLK

3.3V

3.3V

Differential

Input

R5

3.3K

Ω

3.3V

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

R4

6.65K

Ω

3.3V

R1

50

Ω

R2

50

Ω

R3

50

Ω

3.3V

R1

100

Ω

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω

R2

3.3K

Ω

3.3V

R3

3.3K

Ω

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

Ω

R2

120

Ω

R3

120

Ω

R4

113

Ω