ICS843SDN

FEMTOCLOCK™CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR

IDT™ / ICS™ 3.3V LVPECL CLOCK GENERATOR

10

ICS843SDNAG REV. A

NOVEMBER 13, 2012

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 6.

Figure 6. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage

of VCC – 2V.

•

For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCC_MAX – VOH_MAX) = 0.9V

•

For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V

(VCC_MAX – VOL_MAX) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =

[(2V – 0.9V)/50

] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =

[(2V – 1.7V)/50

] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

V

OUT

V

CC

V

CC - 2V

Q1

RL

50

Ω