MPC93R51

REVISION 4 MARCH 14, 2016

5

©2013 Integrated Device Technology, Inc.

MPC93R51 Data Sheet

LOW VOLTAGE PLL CLOCK DRIVER

Table 6. AC Characteristics (VCC = 3.3 V  5%, TA = 0° to 70°C)

(1)

1. AC characteristics apply for parallel output termination of 50

 to V

TT.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency(2)

 4 feedback

 8 feedback

Static test mode

2. The PLL will be unstable with a divide by 2 feedback ratio

50

25

0

120

60

300

MHz

MHz

MHz

PLL_EN = 1

PLL_EN = 1

PLL_EN = 0

fVCO

VCO Frequency

200

480

MHz

fMAX

Maximum Output Frequency(2)

 2 output

 4 output

 8 output

100

50

25

240

120

60

MHz

MHz

MHz

frefDC

Reference Input Duty Cycle

25

75

%

VPP

Peak-to-Peak Input Voltage

PCLK, PCLK

500

1000

mV

LVPECL

VCMR

(3)

3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range

and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().

Common Mode Range

PCLK, PCLK

1.2

VCC–0.9

V

LVPECL

tr, tf

(4)

4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf

are within the specified range.

TCLK Input Rise/Fall Time

1.0

ns

0.8 to 2.0 V

t()

Propagation Delay (static phase offset)

TCLK to EXT_FB

PCLK to EXT_FB

-50

+25

+150

+325

ps

ps

PLL locked

PLL locked

tsk(o)

Output-to-Output Skew

150

ps

DC

Output Duty Cycle

100 – 240 MHz

50 – 120 MHz

25 – 60 MHz

45

47.5

48.75

50

50

50

55

52.5

51.75

%

%

%

tr, tf

Output Rise/Fall Time

0.1

1.0

ns

0.55 to 2.4 V

tPLZ, HZ

Output Disable Time

7.0

ns

tPZL, ZH

Output Enable Time

6.0

ns

BW

PLL closed loop bandwidth

 4 feedback

 8 feedback

3.0 – 9.5

1.2 – 2.1

MHz

MHz

–3 db point of

PLL transfer characteristic

tJIT(CC)

Cycle-to-cycle jitter

 4 feedback

Single Output Frequency Configuration

10

22

ps

RMS value

tJIT(PER)

Period Jitter

 4 feedback

Single Output Frequency Configuration

8.0

15

ps

RMS value

tJIT()

I/O Phase Jitter

4.0 – 17

ps

RMS value

tLOCK

Maximum PLL Lock Time

1.0

ms