ADM1062ASU datasheet(16/32 Pages) AD

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ADM1062

Preliminary Technical Data

Rev. PrJ | Page 16 of 32

expected supervisory range limits (though not above 6V as this

would violate the absolute maximum ratings on these pins). For

instance a 1.5V supply connected to the VX1 pin would

correctly read out as an ADC code of approximately 3/4 Full

scale but would always sit above any supervisory limits that

could be set on that pin.

It is not possible to set REFIN to higher than 2.048V.

VXN PINS AS DIGITAL INPUTS

As outlined previously, the VXn inputs pins on the ADM1062

have dual functionality. The second function is as a digital input

to the device. Thus, the ADM1062 can be configured to have up

to five digital inputs. These inputs are TTL/CMOS compatible.

Standard logic signals can be applied to the pins: RESET from

reset generators, PWRGOOD signals, fault flags, manual resets,

and so on. These signals are available as inputs to the SE, and so

can be used to control the status of the PDO’s. The inputs can

be configured to detect either a change in level or an edge.

When configured for level detect, the output of the digital block

is simply a buffered version of the input. When configured for

edge detect, once the logic transition is detected, a pulse of

programmable width is outputted from the digital block. The

width is programmable from 0µs to a maximum of 100µs. The

digital blocks feature the same glitch filter function available on

the SFD’s. This enables the user to ignore spurious transitions

on the inputs. For example, the filter can be used to debounce a

manual reset switch. When configured as digital inputs, each of

the VXn pins has a weak (10µA) pull-down current source

available for placing the input in a known condition, even if left

floating. The current source, if selected, weakly pulls the input

to GND.

Figure 25. VXn Digital Input Function

ADM1062ASU Datasheet(PDF) 16 Page - Analog Devices