ISL85012 datasheet(13/21 Pages) RENESAS

13 / 21 page

ISL85009

FN8918 Rev.3.00

Page 13 of 20

Nov 11, 2021

Light-Load Operation

The ISL85009 monitors both the current in the low-side MOSFET

and the voltage of the FB node for regulation. Pulling the SYNC

pin low allows the regulator to enter discontinuous operation

when lightly loaded by operating the low-side MOSFET in Diode

Emulation Mode (DEM). In this mode, reverse current is not

allowed in the inductor and the output falls naturally to the

regulation voltage before the high-side MOSFET is switched for

the next cycle. In CCM mode, the boundary is set by Equation 1:

where D = duty cycle, fSW = switching frequency, L = inductor

value, IOUT = output loading current, VOUT = output voltage.

Table 3 shows the operating modes determined by the SYNC pin.

Switching Frequency Setting and

Synchronization

The ISL85009’s switching frequency can be set by the FREQ pin.

Floating the FREQ pin sets the switching frequency to 600kHz,

while shorting the FREQ pin to ground sets the switching

frequency to 300kHz. The ISL85009 can also be synchronized

from 100kHz to 1MHz by an external signal applied to the SYNC

pin. The rising edge on the SYNC triggers the rising edge of the

PHASE pulse. Make sure the on-time of the SYNC pulse is longer

than 100ns.

When floating the FREQ pin for 600kHz switching frequency, or

using synchronizing to an external clock on the SYNC pin, along

with the internal compensation option (COMP short to GND

through a 200Ω resistor), the voltage loop is internally

compensated with a 30pF and 800kΩ RC network. A 30pF and

1200kΩ RC network is implemented for internal compensation

when It works with FREQ = GND (fSW = 300kHz).

In applications, the minimum on-time requirement of the

regulator limits the range of the switching frequency. The

maximum switching frequency can be calculated using

Equation 2:

ISL85009 requires a minimum on-time of 150ns (maximum) for

proper output regulation. For example, with 1V output voltage

and 18V maximum input voltage, the switching frequency must

be less than 370kHz.

Output Voltage Selection

The regulator output voltages can be programmed using external

resistor dividers that scale the voltage feedback relative to the

internal reference voltage. The scaled voltage is fed back to the

inverting input of the error amplifier; refer to Figure 33.

The output voltage programming resistor, R2, will depend on the

value chosen for the feedback resistor, R1, and the desired

output voltage, VOUT; see Equation 3. The R1 value will

determine the gain of the feedback loop. See “Loop

Compensation Design” on page 16 for more details. The value for

the feedback resistor is typically between 1kΩ and 370kΩ.

If the desired output voltage is 0.6V, then R2 is left unpopulated.

R1 is still required to set the low frequency pole of the modulator

compensation.

Protection Features

The regulator limits current in all on-chip power devices.

Overcurrent limits are applied to the two output switching

MOSFETs as well as to the LDO linear regulator that feeds VDD.

The output overvoltage protection circuitry on the switching

regulator provides a second layer of protection.

High-Side MOSFET Overcurrent Protection

Current flowing through the internal high-side switching MOSFET

is monitored during on-time. The current, which is temperature

compensated, will compare to a default 15A overcurrent limit.

The ISL85009 offers two OCP schemes to implement the

on-time overcurrent protection, which can be configured by the

MODE pin (see Table 4).

If the measured current exceeds the overcurrent limit, the high-side

MOSFET is immediately turned off and will not turn on again until

the next switching cycle. After eight consecutive cycles of

overcurrent events detected, the converter will operate at the

selected OCP scheme according to the MODE pin configuration. A

cycle where an overcurrent condition is not detected will reset the

counter.

The switching frequency will be folded back if the OCP is tripped

and the on-time of the PWM is less than 250ns to lower down the

average inductor current.

TABLE 3. OPERATION MODE SETTING

SYNC PIN SETTING

LIGHT-LOAD OPERATION

Float

Forced CCM

GND

DEM

IOUT

VOUT 1D

–



2LfSW

-----------------------------------

(EQ. 1)

fSW Max



VOUT

VIN MAX

 minton



--------------------------------------------------

(EQ. 2)

FIGURE 33. EXTERNAL RESISTOR DIVIDER

TABLE 4. OCP SCHEME SETTING

MODE PIN SETTING

OCP SCHEME

Float

Enter Hiccup mode after eight consecutive

cycle-by-cycle limits. Blanking time is 150ms.

GND

Enter Latch-Off mode after eight consecutive

cycle-by-cycle limits.

R1 0.6V



VOUT 0.6V

–

----------------------------------

(EQ. 3)

0.6V

REFERENCE

VOUT

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