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ISL98607 Datasheet(PDF) 14 Page - Renesas Technology Corp

Part # ISL98607
Description  High Efficiency Power Supply for Small Size Displays
PDF  29 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL98607 Datasheet(HTML) 14 Page - Renesas Technology Corp

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ISL98607
4. Application Information
FN8421 Rev.1.00
Page 14 of 29
Jun.3.19
4.5.2.1 Output Voltage Calculation
The expected output voltage for each regulator is determined using Equations 1 through 3. For the calculations:
VBST = 5.15V (typical) default, VP = +5V (typical) default, VN = -5V (typical) default. Note: VBST_OUT, VP_OUT,
and VN_OUT are the respective 5-bit register settings in decimal.
• Boost Output Voltage, VBST:
• LDO Output Voltage, VP
• Negative Charge Pump Output Voltage, VN:
Example Calculations:
If VBST_OUT = 10 (dec):
If VP_OUT = 10 (dec):
If VN_OUT = 10 (dec):
4.5.3 VBST_CNTRL, VN_CNTRL
In addition to output voltages adjustments, key operation parameters are changed using the I2C to optimize the
ISL98607 performance.
The “VBST_CNTRL” register (Register Address 0x0D) controls and optimizes boost PFM mode, boost FET slew
rate, and switching frequency of the boost and charge pump.
The VN_CNTRL register (Register Address 0x0F) enables and disables the PFM mode, and optimizes the charge
pump PFM operation with adjustments to the PFM peak current, and pulse length.
4.5.4 FAULT
The “FAULT” register (Register Address 0x04) reads back the current fault status of the IC. The fault conditions
that are read back by I2C are:
• VBST undervoltage fault
• VP undervoltage fault
• VN undervoltage fault
• Over-Temperature Protection (OTP)
FAULT register bits <b3:b0> are reset by cycling the logic voltage on both the ENP and ENN pins simultaneously
(set ENN = ENP = LOW, then ENN = ENP = HIGH) or power cycling VIN.
If FAULT register bit <b0> (OTP status bit) is latched HIGH for an OTP fault, it is reset after it is read twice by the
I2C. A single I2C read returns the bit value (status), and a second read resets only the OTP bit.
VBST V

VBST VBST_OUT 50mV
+
=
(EQ. 1)
VP V

VP VP_OUT 50mV
+
=
(EQ. 2)
VN V

VN VN_OUT 50mV
–
=
(EQ. 3)
VBST V

5.15V 10 50mV
+
5.65V
==
VP V

5V 10 50mV
+
5.5V
==
VN V

-5V 10 50mV
–
-5.5V
==



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