DLPC3426ZVB datasheet(39/68 Pages) TI

39 / 68 page

DMD_LS_RDATA

DMD_LS_CLK

DMD_HS_WDATA_B_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_C_P

High Speed sub-LVDS DDR Interface

DMD_HS_WDATA_D_N

DMD_HS_WDATA_D_P

DMD_HS_CLK_N

DMD_HS_CLK_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_A_P

Sub-LVDS-DMD

(Example DMD)

DLP230xx

960 x 540 display

Low Speed SDR Interface (120 MHz)

DLPC34xx

DMD_LS_WDATA

DMD_DEN_ARSTZ

Figure 7-11. DLP230NP/NPSE (.23 Full HD) DMD Interface Example

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34x6 controller depends on the

total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,

and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires

attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control

and Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both

waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).

Variation from these recommendations may also work, but should be confirmed with PCB signal integrity

analysis or lab measurements.

7.4 Device Functional Modes

The DLPC34xx controller has two functional modes (ON and OFF) controlled by a single pin, PROJ_ON

(GPIO_08).

• When the PROJ_ON pin is set high, the controller powers up and can be programmed to send data to the

DMD.

• When the PROJ_ON pin is set low, the controller powers down and consumes minimal power.

7.5 Programming

The DLPC34xx controller contains an Arm® Cortex®-M3 processor with additional functional blocks to enable

video processing and control. TI provides software as a firmware image. The customer is required to flash this

firmware image onto the SPI flash memory. The DLPC34xx controller loads this firmware during startup and

regular operation. The controller and its accompanying DLP chipset requires this proprietary software to operate.

The available controller functions depend on the firmware version installed. Different firmware is required for

different chipset combinations (such as when using different PMIC devices). See Documentation Support at the

end of this document or contact TI to view or download the latest published software.

Users can modify software behavior through I2C interface commands. For a list of commands, view the software

user's guide accessible through the Documentation Support page.

www.ti.com

DLPC3436

DLPS156E – JANUARY 2019 – REVISED APRIL 2023

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DLPC3426ZVB Datasheet(PDF) 39 Page - Texas Instruments

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