DSP56004ROM datasheet(49/82 Pages) NXP

49 / 82 page

Specifications

Serial Host Interface (SHI) SPI Protocol Timing

MOTOROLA

DSP56004/D, Rev. 3

2-25

153 SCK Edge to Data Out

Not Valid

(Data Out Hold Time)

master

slave

bypassed

narrow

wide

bypassed

narrow

wide

163

—

163

—

163

—

154 SS Assertion to Data

Out Valid

CPHA = 0

slave

TC + TH + 35

—

53.5

157 First SCK Sampling

Edge to HREQ

Output Deassertation

slave

bypassed

narrow

wide

× T

C + TH + 32

× T

C + TH +

209

× T

C + TH +

507

—

102

279

577

—

262

560

—

252

550

158 Last SCK Sampling

Edge to HREQ

Output Not

Deasserted

CPHA = 1

slave

bypassed

narrow

wide

× T

C + TH + 6

× T

C + TH + 63

× T

C + TH +

169

113

219

—

101

207

—

36.9

93.9

200

—

159 SS Deassertation to

HREQ Output Not

Deasserted

CPHA = 0

slave

× T

C + TH + 7

37.9

160 SS Deassertation

Pulse Width CPHA =

slave

TC + 4

—

16.3

—

161 HREQ In Assertion to

First SCK Edge

master

0.5

× t

SPICC+

× T

C + 6

106

—

67.7

—

162 HREQ In

Deassertation to Last

SCK Sampling Edge

(HREQ In Set-up

Time) CPHA = 1

master

0—0—

—

Table 2-12

Serial Host Interface (SHI) SPI Protocol Timing (Continued)

No.

Characteristics

Mode

Filter

Mode

Expression

50 MHz

66 MHz

81 MHz

Unit

Min Max Min Max Min

Max

Freescale Semiconductor, Inc.

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