BOARD LAYOUT FLOW

1.

Minimize C1, PV

and PGND loop. These traces

should be as wide and short as possible. This is most

important.

2.

Minimize L1, C2, SW and PGND loop. These traces also

should be wide and short. This is the second priority.

3.

Above layout patterns should be placed on the compo-

nent side of the PCB to minimize parasitic inductance

and resistance due to via-holes. It may be a good idea

that the SW to L1 path is routed between C2(+) and

C2(-) land patterns. If vias are used in these large cur-

rent paths, multiple via-holes should be used if possible.

4.

Connect C1(-), C2(-) and PGND with wide GND pattern.

This pattern should be short, so C1(-), C2(-), and PGND

should be as close as possible. Then connect to a PCB

common GND pattern with as many via-holes as pos-

sible.

5.

SGND should not connect directly to PGND. Connecting

these pins under the device should be avoided. (If pos-

sible, connect SGND to the common port of C1(-), C2(-)

and PGND.)

6.

FB line should be protected from noise. It is a good idea

to use an inner GND layer (if available) as a shield.

7.

The LDO Cap C7 (C

the PA as possible and as far away from the switcher to

suppress high frequency switch noises.

Note: The evaluation board shown in Figure 5 for the LM3207 was designed

with these considerations, and it shows good performance. However

some aspects have not been optimized because of limitations due to

evaluation-specific requirements. Please refer questions to a National

representative.

20165357

FIGURE 5. Evaluation Board Layout

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