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MPC105EC/D Datasheet(PDF) 9 Page - NXP Semiconductors

Part # MPC105EC/D
Description  MPC105 PCI Bridge/Memory Controller Hardware Specifications
PDF  24 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC105EC/D Datasheet(HTML) 9 Page - NXP Semiconductors

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105 Hardware Specifications
9
Preliminary/Subject to Change without Notice
25
SYSCLK to output invalid
(output hold)
0.0
—
ns
26
SYSCLK to output high impedance (all except ARTRY)
—
8.0
ns
27
SYSCLK to ARTRY high impedance before precharge
(output hold)
—
8.0
ns
28
SYSCLK to ARTRY precharge enable (1X, 2X, PLL mode)
0.4 * tSYS
+ 2.0
—
ns
5, 6
29
Precharge width for ARTRY
1.0
t
SYS
5, 6
30
SYSCLK to ARTRY high impedance after precharge (1X,
2X PLL modes)
—
1.5 * tSYS
+ 8.0
ns
5
Notes:
All output specifications are measured from the TTL level (0.8 V or 2.0 V) of the signal in question to the
1.4 V of the rising edge of SYSCLK. Processor and memory interface signals are specified from the rising
edge of the processor and memory bus clock, which is the same as SYSCLK in 1:1 mode, but is twice the
frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of
SYSCLK). Both input and output timings are measured at the pin.
1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level
(0.8 V or 2.0 V) of the signal in question. The output timings are measured at the pin.
2. Maximum timing specifications assume CL = 50 pF.
3. PCI bus signals are composed of the following signals—LOCK, MEMACK, ISA_MASTER,
C/BE0–C/BE3, PAR, TRDY, FRAME, STOP, DEVSEL, PERR, SERR, and AD0–AD31.
4. PCI point-to-point signals are composed of the GNT signal.
5. tSYS is the period of the external bus clock (SYSCLK) in nanoseconds. The numbers given in the table
must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the
parameter in question.
6. These specifications are nominal values.
7. Shared outputs, TS and ARTRY, require pull-up resistors to hold them negated when there is no bus
master driving.
Table 7. Output AC Timing Specifications (Continued)
Vdd = 3.3
± 5% Vdc, GND = 0 Vdc
Num
Characteristic
Min
Max
Unit
Notes
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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