PowerPC 602 RISC Microprocessor Hardware Specifications

9

Figure 1. SYSCLK Input Timing Diagram

1.3.2.2 Input AC Specifications

Table 7 provides the input AC timing specifications for the 602.

8

SYSCLK short-term jitter

(cycle-to-cycle)

—

±150

—

±150

ps

4

9

602 internal PLL relock time

—

100

—

100

µs

5,6

Notes:

1. Times shown in specifications are only valid for a 66.67 MHz processor frequency.

2. PLL_CFG settings that cause the VCO or processor to operate outside of specified range are not

guaranteed. Recommended PLL_CFG0–PLL_CFG3 settings for 2:1 mode are—66 MHz - 0101; 80

MHz - 0101. Recommended PLL_CFG0–PLL_CFG3 settings for 3:1 mode are—66 MHz - 1001; 80

MHz - 1001.

3. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.

4. This parameter shows the sum of short- and long-term jitter. Short- and long-term jitter are

guaranteed by design.

5. Timing is guaranteed by design and characterization, and is not tested.

6. PLL-relock is the maximum time required for the PLL to lock after Vdd and SYSCLK become stable

during power-on reset or wake-up from sleep mode. During the power-on-reset sequence, HRESET

must be asserted for a minimum of 255 bus clocks after the PLL-relock time.

Table 7. Input AC Timing Specifications

Vdd = 3.3

± 10% V dc, GND = 0 V dc, 0 ≤ T

J ≤ 105 °C

Num

Characteristic

66.67 MHz CPU

Clock

80 MHz CPU

Clock

Unit

Notes

Min

Max

Min

Max

10a

Inputs valid to SYSCLK (input setup)

6

—

6

—

ns

1

10b

Mode select inputs valid to HRESET (input

setup) (for QACK )

8 * tsys

—

8 * tsys

—

ns

1,2,3,4,5

11a

Inputs invalid (input hold)

3.0

—

3.0

—

ns

1

Table 6. Clock AC Timing Specifications (Continued)

Vdd = 3.3

± 10% V dc, GND = 0 V dc, 0 ≤ T

J ≤ 105 °C

Num

Characteristic

66.67 MHz CPU Clock

80 MHz CPU Clock

Unit

Notes

Min

Max

Min

Max

VM

CVil

CVih

SYSCLK

VM = Midpoint Voltage (1.4V)

2

3

1

Freescale Semiconductor, Inc.

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