ADAV400KSTZ datasheet(31/36 Pages) AD

31 / 36 page

ADAV400

Rev. 0 | Page 31 of 36

AUDIO CORE CONTROL REGISTER

The bits in this register control the operation of the DSP core of

the ADAV400 (see Table 29).

Enable SDO2 and SDO3 (Bit 14)

This bit is set to 1 by default and can be used to disable SDO2

and SDO3 if required.

Slew RAM Muted (Bit 13)

This bit is set to 1 when the slew RAM mute operation has been

completed. This bit is read-only and is automatically cleared

by reading.

Write Zero to Target RAM (Bit 12)

Setting this bit to 1 is equivalent to writing 0s to all locations in

the target RAM. This effectively mutes any slew RAMs, such as

volume controls used in a signal flow. To enable normal

operation, clear this bit to 0.

Clear Registers to All Zeros (Bit 9)

Setting this bit to 0 sets the contents of the accumulators and

serial output registers to 0. This bit defaults to 0; therefore, the

ADAV400 powers up in clear mode and does not pass signals

until a 1 is written to this bit. This is intended to prevent noises

from inadvertently occurring during the power-up sequence.

Force Multiplier to Zero (Bit 8)

When this bit is set to 1, the input to the DSP multiplier is set to

0, which results in the multiplier output being 0. This control bit

is included for maximum flexibility and is normally not used.

Initialize Data Memory with Zeros (Bit 7)

Setting this bit to 1 initializes all data memory locations to 0.

This bit is cleared to 0 after the operation is complete. Assert

this bit after a complete program/parameter download has

occurred to ensure click-free operation.

Zero Serial Input Port (Bit 6)

When this bit is set to 1, all input channels to the DSP core are

forced to all 0s, effectively muting the output.

Initiate Safe Transfer to Target RAM (Bit 5)

Setting this bit to 1 initiates a safeload transfer to the target/slew

RAM. This bit clears when the operation is complete. Of five

safeload register pairs (address/data), only those registers that have

been written since the last safeload event occurred are transferred.

Address 0 corresponds to the first target RAM location.

Initiate Safe Transfer to Parameter RAM (Bit 4)

Setting this bit to 1 initiates a safeload transfer to the parameter

RAM. This bit clears when the operation is complete. Of five

safeload registers pairs (address/data), only those registers that have

been written since the last safeload event occurred are transferred.

Address 0 corresponds to the first parameter RAM location.

Program Length (Bits [1:0])

96 kHz and 192 kHz Modes

These bits set the length of the internal program. The default

program length is 2560 instructions for fS = 48 kHz, but the

program length can be shortened by factors of 2 to accommodate

sample rates higher than 48 kHz. For fS = 96 kHz, set the

program length to 1280 (01), and for fS = 192 kHz, set the

length to 640 steps (10).

Note that this is only valid for digital inputs and outputs.

ADAV400KSTZ Datasheet(PDF) 31 Page - Analog Devices

ADAV400KSTZ Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL