Final/Production Release Information - The information contained in this docu-

ment is about a product in its fully tested and characterized phase.All features

described herein are supported. Contact AMCC for updates to this document and

the latest product status

Empowering Intelligent Optical Networks

Product Brief

ORINOCO

STS-12/STM-4 DS3/E3/STS-1E SONET/SDH Mapper

Part Number S1204CBI21, Revision 1.5, Dec. 2002

Features

• Processes any valid combination of SONET/SDH STS-1/AU-3 or

TUG-3/AU-4 tributaries in STS-12/STM-4 or STS-3/STM-1.

• Terminates/generates SONET/SDH section, line, and path OH

• Provides on the SONET/SDH side a serial 622 MHz or a 77.76

MHz 8-bit interface for STS-12/STM-4 applications; or a serial

155.52 MHz interface for STS-3/STM-1 applications.

• Supports flexible assignment of STS-1E and DS3 or STS-1E and

E3 mappings on a per tributary basis.

• Provides STS-1E mapping/demapping for up to 12 STS-1s.

• Provides DS3 or E3 mapping/demapping for up to 12 tributaries,

through SONET STS1, SDH AU-3, and/or TUG-3/AU-4 containers.

• Supports mixed M23 and C-bit parity DS3 frame formats on a per-

tributary basis.

• Supports mixed G.751 and G.832 E3 frame formats on a per-

tributary basis.

• Supports full-featured DS3/E3/STS-1E performance monitoring in

both transmit and receive directions.

• 12 serial clock/data ports are provided on the system side for DS3/

E3/STS-1E interfaces.

• Integrates DS3/E3 desynchronizer circuitry necessary to provide

DS3/E3 clear channel outputs that meet Bellcore, ANSI and ITU

jitter requirements.

• 622/155 MHz APS interface for redundancy applications.

• Loopback capability for SONET/SDH and DS3/E3/STS-1Es data

streams.

The ORINOCO is a highly integrated chip that implements

SONET/SDH processing and DS3/E3/STS-1E mapping functions

for an STS-12/STM-4 or STS-3/STM-1 data stream. The

ORINOCO is compliant with the following standards: Bellcore GR-

253, GR-499 and GR-820; ANSI T1.105 and T1.107; and ITU

G.751-2; G.775, G.783, G.804, G.823-5, and G.832.

The ORINOCO supports full-duplex processing of SONET/SDH

data streams with section, line, & path overhead processing. The

device supports framing, scrambling/descrambling, alarm signal

insertion/detection, and bit interleaved parity (B1/B2/B3)

processing. Serial interfaces for E1, E2, F1 and Line and Section

DCC are also provided.

A general purpose microprocessor interface is provided for device

initialization, control, and monitoring. This interface can operate

either as an 8-bit asynchronous interface, or a 16-bit synchronous

interface. The interface supports both Intel and Motorola type

microprocessors, and is capable of operating in either an interrupt

driven or polled-mode configuration.

Figure 1: Block Diagram

PTR

POH

MONITOR

TOH DROP

TOH

MON

RX

FRAMER

TX

FRAMER

TOH INSERT

SPE/VC

GENERATE

MICROPROCESSOR I/F

GPIO REG

TX_PDATA_OUT_[7:0]

TX_PCLK_OUT

RX_PDATA_IN_[7:0]

RX_PCLK_IN

RX_LOSEXT

1

12

1

12

1

12

DS3/E3

FR

RX_LS_[1:4]_[1:3]_DATA

RX_PFRM_IN

RX_LS_[1:4]_[1:3]_CLK

Intrfc

Intrfc

RX_LS_[1:4]_[1:3]_FRM_OUT

PM

TX_SDATA_OUT

TX_SCLK_OUT

RX_SDATA_IN

RX_SCLK_IN

RX_LINE_PRTY

TX_LINE_PRTY

FR/TOH

MON

SEL

INTPRT

STS-1

FR

GEN

DeSynchronization

RX

1

12

SEL

TX_LS_[1:4_][1:3]_DATA

TX_LS_[1:4]_[1:3]_CLK

TX_LS_[1:4]_[1:3]_FRM_IN

FIFO

STS-1

PTR

PROC

STS-1

Dmap

DS3

1

12

DS3/E3

Frame Generator

1

12

DS3

MAP

E3

TX

1

12

DS3/E3

FR

PM

1

12

DS3/E3

DMAP

1

1

Block