8.3 Feature Description

8.3.1 Enable and Shutdown Input (EN/SHDN)

The TPS1641x devices include a enable and shutdown input. Keeping EN/SHDN low for a duration more than

tLow_SHDN brings the device into low power shutdown mode, internal blocks of device are turned off, and the

quiescent current of the device is reduced to IQSD from Vcc supply.

While keeping EN/SHDN low for a duration less than tLow_SHDN, the device turns off the internal FET only and

FET can be turned back on quickly. The device turns off the internal FET with a delay of tEN_OFF_dly as the

enable pin is brought low. The internal FET can be enabled quickly with a delay of tEN_ON_dly when the device is

not in shutdown. See the Section 7.5 for VENR and VENF thresholds and the Section 7.6 for tLow_SHDN, tEN_OFF_dly,

and tEN_ON_dly timings. A PWM signal with low period less than tLow_SHDN can be provided on EN/SHDN pin of

the device for fast turn-on and turn-off of internal FET. Figure 8-1 illustrates the EN/SHDN input in the TPS1641x

devices. Figure 8-2 shows the start-up of the device with enable input.

TPS1641x

EN/SHDN

+

V

ENR

V

ENF

VINT

EN/SHDN

OFF

ON

Figure 8-1. EN/SHDN in TPS1641x Devices

VIN = 12 V

Figure 8-2. Turn-On with Enable

8.3.2 Overvoltage Protection (OVP)

The TPS1641x implements overvoltage protection to protect the load from input overvoltage conditions. A

resistor divider can be connected from the IN pin of device to configure the overvoltage protection setpoint. The

device turns off the internal FET and asserts the FLT pin as the voltage at OVP pin goes above VOVPR, and

as the OVP pin voltage falls below VOVPF, the internal FET is turned ON and FLT pin is de-asserted. See the

Section 7.5 table for VOVPF and VOVPR and Section 7.6 for tOVP_entry_dly and tOVP_exit_dly timings for overvoltage

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TPS1641

SLVSGF4B – JUNE 2022 – REVISED MAY 2023

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Product Folder Links: TPS1641