CS5320 datasheet(118/160 Pages) AMCC

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S5320 – PCI Match Maker: Pass-Thru Operation

118

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

Figure 64. PCI to Add-On Passive Burst Write

Figure 64 shows a Passive mode PCI to Add-On burst

write of four DWORDs. In the following example, Add-

On logic incorporates the use of PTADR# followed by

multiple data reads to the S5320. If Add-On logic does

not support burst accesses, PTADR# can be pulsed

for individual data reads. The S5320 automatically

increments the address in the APTA register during

PCI bursts. In this example PTRDY# is continually

asserted, indicating that Add-On logic is capable of

accepting one DWORD per clock cycle. In addition,

the PTBE[3:0] signals indicate a unique byte-enable

for each data transfer.

The Pass-Thru Write FIFO (or APTD) can be disabled

for bursts (do not accept PCI posted writes). In this

case, the PCI is allowed to write to only one FIFO

location and cannot continue bursting until the add-on

has read the data. PTBURST# is never asserted when

the PCI write FIFO is disabled. For this example, the

Write FIFO is enabled.

Clock 0:

The address is recognized as a PCI write to

Pass-Thru region 1. The PCI bus write address is

stored in the Pass-Thru Address Register. The PCI

bus write data is stored in the S5320 write FIFO. Add-

On bus signals PTATN#, PTBURST#, PTNUM[1:0],

PTWR and PTBE[3:0] will update on the next rising

edge of ADCLK.

Clock 1:

Pass-Thru signals PTATN#, PTBURST#,

PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-

cate what action is required by Add-On logic. These

status signals are valid only when PTATN# is active.

Add-On logic can decode status signals upon the

assertion of PTATN#.

PTATN# Asserted. Indicates Pass-Thru access is

pending.

PTBURST# Asserted. The access has multiple data

phases.

PTNUM[1:0] 3h. Indicates the access is to Pass-Thru

region 3.

PTWR Asserted. Indicates the access is a write.

PTBE[3:0]# D1. Indicates valid bytes for the first data

transfer.

Clock 2:

The PTADR# input is asserted to read the

Pass-Thru Address Register. The RD#, BE#, ADR[6:2]

and SELECT# inputs are driven during this clock to

read the Pass-Thru Data Register contents onto the

DQ bus during the next clock. PTRDY# is asserted,

indicating that the first transfer is complete.

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]

SELECT#

ADR[6:2]

BE[3:0]#

RD#

DQ[31:0]

PTADR#

ADDR

PTRDY#

DATA1

DATA2

DATA3

2Ch

DATA4

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