CS5320 datasheet(123/160 Pages) AMCC

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S5320 – PCI Match Maker: Pass-Thru Operation

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

123

Data Sheet

Clock 3:

The Add-On logic will latch the Pass-Thru

address on the rising edge of this clock. This cycle is

also required to avoid contention on the DQ bus. Time

must be allowed after PTADR# is deasserted for the

DQ outputs to float before Add-On logic attempts to

write to the Pass-Thru Read FIFO.

Clock 4:

The BE[3:0]#, ADR[6:2], and SELECT#

inputs are asserted. WR# and DQ are asserted, indi-

cating that DATA1 is to be written to the PT Read FIFO

on the next clock. PTRDY# is asserted, to indicate the

completion of the current data phase.

Clock 5:

As the S5320 samples WR# asserted, it

writes DATA1 into the PT Read FIFO. PTRDY# is sam-

pled asserted, which completes the first data transfer

and updates the internal FIFO pointers. The PTBE#

outputs are updated to indicate which bytes are valid

for the second transfer. The Add-On logic samples

PTBURST# asserted, so it knows more data is being

requested. The Add-On keeps WR# asserted, and

drives DATA2 onto the DQ bus. PTRDY# is also

asserted to complete the current data phase.

Clock 6:

As the S5320 samples WR# asserted, it

writes DATA2 into the PT Read FIFO. PTRDY# is sam-

pled asserted, which completes the second data

transfer and updates the internal FIFO pointers. The

PTBE# outputs are updated to indicate which bytes

are valid for the third transfer. The Add-On logic sam-

ples PTBURST# asserted, so it knows more data is

being requested. The Add-On keeps WR# asserted,

and drives DATA3 onto the DQ bus. PTRDY# is also

asserted to complete the current data phase.

Clock 7:

As the S5320 samples WR# asserted, it

writes DATA3 into the PT Read FIFO. PTRDY# is sam-

pled asserted, which completes the third data transfer

and updates the internal FIFO pointers. The PTBE#

outputs are updated to indicate which bytes are valid

for the last transfer. The S5320 deasserts PTBURST#,

indicating that the previous read was the second to

last. The next transfer from the Add-On bus will be the

last. The Add-On logic samples PTBURST# asserted,

so it knows more data is being requested. The Add-On

keeps WR# asserted, and drives DATA4 onto the DQ

bus. PTRDY# is also asserted to complete the current

data phase.

Clock 8:

As the S5320 samples WR# asserted, it

writes DATA4 into the PT Read FIFO. PTRDY# is sam-

pled asserted, which completes the final data transfer

and updates the internal FIFO pointers. The S5320

deasserts PTATN#, indicating that the final transfer

was performed. No more data is being requested from

PCI. The Add-On logic samples PTBURST# deas-

serted, so it knows that the previous data transfer was

the last, and no more data is being requested. The

Add-On deasserts WR#, ADR[6:2], SELECT#,

BE[3:0]# and DQ. It also deasserts PTRDY#. Note that

in a synchronous design, the Add-On logic does not

require PTATN# in order to terminate a Pass-Thru

read operation, PTBURST# is used for this.

Clock 9:

As PTATN# and PTBURST# are deasserted,

the Pass-Thru access is complete, and the S5320 can

accept new Pass-Thru accesses starting on the next

clock. The other Pass-Thru signals can also change

state (in anticipation of a new transfer).

NOTE:

With prefetch disabled, the performance of

Pass-Thru burst reads will be less than optimal.

Because of certain issues involving synchronizing sig-

nals across clock boundaries (ADCLK -> PCLK),

Pass-Thru burst reads will occur only in double and

single accesses. For example, a Pass-Thru burst read

of five data phases would translate to a burst-read of

two DWORDs, another burst-read of two DWORDs

followed by a single burst-read with PTATN# being

deasserted between each burst packet, losing poten-

tially valuable clock cycles. It is recommended to

enable prefetch if maximum performance is desired.

Figure 67 also shows a Passive Mode Pass-Thru burst

read, but the Add-On logic uses PTRDY# to control

the rate at which data is transferred. In many applica-

tions, Add-On logic is not fast enough to provide data

every ADCLK. In this example, the Add-On interface

writes data every other clock cycle.

Using PTRDY# to assert Wait-States

Clock 0: PCI address information is stored in the Pass-

Thru Address Register. The address is recognized as

a PCI read of Pass-Thru region 1. Add-On bus signals

PTATN#, PTBURST#, PTNUM[1:0], PTWR and

PTBE[3:0] will update on the next rising edge of

ADCLK.

Clock 1:

Pass-Thru signals PTATN#, PTBURST#,

PTNUM[1:0], PTWR and PTBE[3:0] are driven to indi-

cate what action is required by Add-On logic. These

status signals are valid only when PTATN# is active.

Add-On logic can decode status signals upon the

assertion of PTATN#.

PTATN# Asserted. Indicates Pass-Thru access is

pending.

PTBURST# Asserted. The access has multiple data

phases.

PTNUM[1:0] 0h.Indicates. the access is to Pass-Thru

region 0.

PTWR Deasserted. Indicates the access is a read.

PTBE[3:0]# D1. Indicates valid bytes for the first data

transfer.

CS5320 Datasheet(PDF) 123 Page - Applied Micro Circuits Corporation

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