CS5320 datasheet(128/160 Pages) AMCC

128 / 160 page

S5320 – PCI Match Maker: Pass-Thru Operation

128

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

S5320, so BYTE0 of the APTD is driven on DQ[7:0].

PTRDY# is sampled asserted, so the previous transfer

is complete. The PTBE# signals are updated to indi-

cate which bytes are valid for the next transfer (in this

case, there is no more valid data to transfer, so PTBE

= Fh). The S5320 deasserts PTATN#, as it has no data

left to transfer. The Add-On device deasserts RD#,

BE#, ADR[6:2], SELECT# as the data transfer is

complete.

Clock 11:

The Add-On logic latches BYTE0 of the

second DWORD. PTATN# and PTBURST# both deas-

serte d indicate that th e Pass-T hru transfer is

complete. The PCI can start another access on the

next clock cycle. For 16-bit peripheral devices, the

byte steering works in the same way. Because the

Add-On data bus is 16 bits wide, only two 16-bit cycles

are required to access the entire APTD Register. Two

byte enables can be asserted during each access.

Figure 69 shows a Pass-Thru read operation for a

region defined for a 16-bit Add-On bus interface. As

the 16-bit device is connected only to DQ[15:0], the

device must access the APTD one word at a time. The

Add-On must be capable of latching the upper 16 bits

of the APTA (if they are needed).

The PCI initiator has requested a 32-bit burst read

from Pass-Thru region three. All PTBE#s are asserted.

Clock 1:

The Add-On begins by reading the APTA

are driven on the DQ bus.

Clock 2:

Turn-around cycle, preventing potential bus

contention on the DQ bus.

Clock 3:

The Add-On initiates the write by asserting

WR#, SELECT#, BE[3:0]# = “1100”, ADR[6:2] = 2Ch

and the low word of the first DWORD to be transferred

(D0-LO).

Clock 4:

The S5320 updates the PTBE#s to indicate

that the low word was provided, and that the upper

word is still required. The Add-On drives the upper

word (D0-HI), and activates the appropriate byte

enables, BE# = 0011 The Add-On also asserts

PTRDY#, indicating that it is done with the current

DWORD, and to advance the FIFO pointer and pre-

pare for the second DWORD.

Clock 5:

The PTBE#s are updated to indicate that the

next DWORD to be transferred requires all bytes. The

Add-On drives DQ[15:0] with the lower word of the

second DWORD (D1-LO), and the byte-enables indi-

cate the same, BE# = 1100. The Add- On also

deasserts PTRDY#. This process continues until the

transfer is complete and all words have been written.

Endian Conversion

Endian conversion can be enabled/disabled for each

Pass-Thru Region. It is controlled by bits 6, 14, 22 and

30 of the PTCR. The default endian type for the S5320

is Little Endian. For this reason, the default values in

the PTCR are for Little Endian. If Big Endian is

selected, the Pass-Thru data and byte-enable inter-

face will be converted to Big Endian type.

When the device is programmed for Big Endian trans-

lation and a 32-bit data bus, the S5320 will convert as

described in Table 45.

Active mode is provided to simplify logic requirements

when interfacing an application to the Add-On Local

bus. Passive mode requires Add-On logic to assert

read/write signals and drive or latch data on the DQ

bus.

Strapping PTMODE low configures the S5320 for

Active mode operation. Active mode allows more

designer flexibility through programmable features.

The following is a brief description of these features.

•

Pass-Thru address can be driven automatically

at the beginning of all transfers or can be

skipped altogether if addresses are unneeded

by Add-On logic.

•

Programmed or Add-On controlled wait states

to delay data transfers automatically or on the

fly.

•

Endian Conversion

•

Write FIFO ( Write posting )

•

Read FIFO ( Prefetch )

Active Operation

In Active mode, a data transfer start is signaled on the

first clock edge in which PTATN# is sampled low. If

PTADR# has been programmed to be output it will go

active (low) at this time, and the data presented on the

DQ bus is the address for the current transaction. Add-

On logic may latch the address value at the rising

edge of the clock. Address cycles do not count toward

the number of wait states needed to complete data

phases. In Active mode, the PTRDY# pin is renamed

to PTWAIT#. On cycles after PTWAIT# is sampled low,

the state machine is idle. Idle cycles are also not

counted as wait states by the S5320. To control the

number of wait states on an as-needed basis only,

zero wait states should be programmed and PTWAIT#

can be driven low when wait states are to be inserted.

If PTWAIT# is low when PTATN# is asserted by the

S5320, the pending transfer cycle won’t be started

until PTWAIT# is driven high.

CS5320 Datasheet(PDF) 128 Page - Applied Micro Circuits Corporation

CS5320 Datasheet(HTML) 128 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL