CS5320 datasheet(131/160 Pages) AMCC

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S5320 – PCI Match Maker: Pass-Thru Operation

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

131

Data Sheet

Active mode Programmable Wait States

Bits 0,1,2 of the PTCR register control this feature.

Wait States are programmed on a per region basis.

For example: region one can be set for zero wait

states while other regions may have multiple wait

states programmed.

Wait state options are 0,1,2,...7 wait states. The S5320

will always count N wait states (N=0,1,..7) before com-

pleting the current data phase.

Figures 76, 77 and 78 show Pass-Thru transfers with

programmed wait states.

PTRDY#/PTWAIT#

In Active mode, the PTRDY#/PTWAIT# pin takes the

PTWAIT# function, which is the opposite function of

this pin when configured for passive mode. That is, if

the part is configured to operate in Active mode,

PTWAIT# asserted low means the Add-On wishes to

insert wait states.

Add-On peripherals are allowed to insert wait state

cycles at any time during an Active mode transfer.

When PTWAIT# has been sampled low, the S5320 will

tri-state its DQ[31:0] bus in order to allow other Add-

On devices to use the bus without contention.

Figure 73. Active Mode PCI Write with Add-On Initiated Wait States Using PTWAIT#

Figure 74. Active Mode 32-Bit PCI Write

The address phase of a Pass-Thru consists of the

cycles from PTATN# asserted through PTADR#

asserted (if PTADR# has been programmed to be dis-

abled, there is no address phase). If PTWAIT# is

asserted before the address phase, the address

phase is delayed. The address phase will occur during

the cycle after the clock edge that PTWAIT# is sam-

pled high and PTATN# is sampled low.

The data phase(s) of a Pass-Thru consists of all the

cycles after the (possibly nonexistent) address phase.

During data phases, a wait is incurred during the cycle

after PTWAIT# is sampled asserted.

Note: If PTWAIT# is activated in order to access other

registers internal to the S5320, the user is responsible

for inserting any needed turnaround cycles in order to

avoid bus contention on the DQ bus.

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]#

DXFR#

DQ[31:0]

PTADR#

PTWAIT#

DATA

PTADDR

01b

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]

DXFR#

DQ[31:0]

PTWAIT#

PTADDR

DATA

PTADR#

01b

234

CS5320 Datasheet(PDF) 131 Page - Applied Micro Circuits Corporation

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