CS5320 datasheet(135/160 Pages) AMCC

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S5320 – PCI Match Maker: Pass-Thru Operation

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

135

Data Sheet

Figure 77. 16-Bit Active Mode PCI Read w/ Programmed Wait States

Clock 2:

Since this region does have PTADR#

enabled as an output, it is driven active (low) and the

PCI address for the current transaction is presented

on the DQ[31:0] bus.

Clock 3:

The Add-On device must latch the PCI

address at the rising edge of this clock.

Clock 4:

DXFR# is asserted low indicating that data

will be transferred on the next rising clock edge (clock

5). Data1 is driven onto the DQ[31:0] bus.

Clock 5:

The Add-On device must latch the first data

word at the rising edge of this clock. Valid data is

determined by decoding the PTBE[3:0]# lines.

Clock 6:

DXFR# is asserted indicating that data will be

transferred on the next rising clock edge (clock 7).

DATA2 is driven onto the DQ[31:0] bus.

Clock 7:

The Add-On side device latches the second

data word (DATA2) at the rising edge of this clock.

Clock 8:

DXFR# is asserted indicating that data will be

transferred on the next rising clock edge (clock 9).

DATA3 is driven onto the DQ[31:0] bus. PTBURST# is

driven inactive indicating that after this data word is

transferred, there is only one data word left to transfer.

Clock 9:

The Add-On side device latches the third

data word (DATA3) at this clock edge.

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]#

DXFR#

DQ[15:0]

PTADR#

PTWAIT#

PTADDR

HIGH

LOW

914

CS5320 Datasheet(PDF) 135 Page - Applied Micro Circuits Corporation

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