CS5320 datasheet(139/160 Pages) AMCC

139 / 160 page

S5320 – PCI Match Maker: Pass-Thru Operation

Revision 5.03 – June 14, 2006

AMCC Confidential and Proprietary

DS1656

139

Data Sheet

After the host reads all Base Address Registers in the

system (as every PCI device implements from one to

six), the PCI BIOS allocates memory and I/O space to

each Base Address region. The host then writes the

start address of each region back into the Base

Address Registers. The start address of a region is

always an integer multiple of the region size. For

example, a 64-Kbyte memory region is always

mapped to begin on a 64K boundary in memory. It is

important to note that no PCI device can be absolutely

located in system memory or I/O space. All mapping is

determined by the system, not the application.

PCI or Add-On Operation registers PTCR or APTCR

provide additional configuration control for each

region.

Accessing a Pass-Thru Region

After the system is finished defining all Base Address

Regions within a system, each Base Address Register

contains a physical address. The application software

must now find the location in memory or I/O space of

its hardware. PCI systems provide BIOS or operating

system function calls for application software to find

particular devices on the PCI bus based on Vendor ID

and Device ID values. This allows application software

to access the device’s Configuration Registers.

The Base Address Register values in the S5320’s

Configuration Space may then be read and stored for

use by the program to access application hardware.

The value in the Base Address Registers is the physi-

cal address of the first location of that Pass-Thru

region. Some processor architectures allow this

address to be used directly to access the PCI device.

For Intel Architecture systems, the physical address

must be changed into a Segment/Offset combination.

For Real Mode operation in an Intel Architecture sys-

tem (device mapped below 1 Mbyte in memory),

creating a Segment/Offset pair is relatively simple. To

calculate a physical address, the CPU shifts the seg-

ment register 4 bits to the left and adds the offset

(resulting in a 20 bit physical address). The value in

the Base Address Register must be read and shifted 4

bits to the right. This is the segment value and should

be stored in one of the Segment registers. An offset of

zero (stored in SI, DI or another offset register)

accesses the first location in the Pass-Thru region.

Special Programming Features

A few additional features have been provided to the

user which will allow for optimal “tuning” of their sys-

tem. As these are not features that will be changed “on

the fly”, they have been included as part of the nvRAM

boot-up sequence. nvRAM address 45h is a memory

location in the external nvRAM which will contain

these custom programmed bits. These features, and

their corresponding bit at location 45h, are described

as follows:

Target Latency describes the number of cycles that a

target device may respond to a PCI data transfer

request. The PCI 2.1 specification indicates that the

target device has 16 clocks to respond to an initial

request (from the assertion of FRAME#), and 8 clocks

from each subsequent data phase. If the target is not

capable of asserting TRDY# within these time frames,

it must assert a STOP#, thus initiating a disconnect.

The Target Latency programmed bit allows the user to

disable the generation of disconnects in the event of a

slow Add-On device.

If Target Latency Enb is low, target latency is ignored.

In this case, the S5320 will never issue a retry/discon-

nect in the event of a slow add-on device. Instead,

TRDY# wait states will be asserted. This might be use-

ful for an embedded system, where the S5320 can

take up as many clock cycles as necessary to com-

plete a transfer. This programmable bit is only

provided for flexibility and most users should leave this

bit set to 1. If Target Latency Enb is high, the device

will be PCI 2.1 compliant with respect to Target

Latency.

Retry Flush Enb indicates to the Pass-Thru whether to

hold prefetched data following a disconnect, or to

allow the data to be flushed out during the next PCI

read access. If low, the data will be held in the PT read

FIFO until the initiator comes back to read it out. All

subsequent PCI accesses to the S5320 from a device

other than the one who initiated the read will be

acknowledged with a retry. If the master never returns

for the data, the Pass-Thru function will be hung. Even

though the PCI 2.1 Specification does not require a

master to return for data following a disconnect, it is

unlikely that a master will terminate a read transfer

until all data has been collected.

If Retry Flush Enb is high, the data will be flushed from

the FIFO if a subsequent PCI read access is not to the

same address. If the original master received a retry

LOC_45(h)

Descripton

Default

b = 0

Target Latency Enb

b = 1

Retry Flush Enb

b = 2

Write FIFO Mode

b = (7:3)

Reserved

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