CS5320 datasheet(138/160 Pages) AMCC

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S5320 – PCI Match Maker: Pass-Thru Operation

138

DS1656

AMCC Confidential and Proprietary

Revision 5.03 – June 14, 2006

Data Sheet

S5320 Base Address Register Definition

Certain bits in the Base Address Register have spe-

cific functions:

BADR1:4 bits D31:30 are used only by the S5320.

When the host reads the Base Address Registers dur-

ing configuration cycles, they always return the same

value as D29. If D29 is zero, D31:30 return zero, indi-

cating the region is disabled. If D29 is one, D[31:30]

return one. This operation limits each Pass-Thru

region to a maximum size of 512 Mbytes of memory.

For I/O mapped regions, the PCI specification allows

no more than 256 bytes per region. The S5320 allows

larger regions to be requested by the Add-On, but a

PCI BIOS will not allocate the I/O space and will prob-

ably disable the region.

Figure 81. 8-Bit Active Mode PCI Write

Creating a Pass-Thru Region

Section 3.11 describes the values that must be pro-

grammed into the non-volatile boot device to request

various block sizes and characteristics for Pass-Thru

regions. After reset, the S5320 downloads the con-

tents of the boot device locations 54h, 58h, 5Ch, and

60h into “masks” for the corresponding Base Address

Registers. The following are some examples for vari-

ous Pass-Thru region definitions:

During the PCI bus configuration, the host CPU writes

all ones to each Base Address Register, and then

reads the contents of the registers back. The mask

downloaded from the boot device determines which

bits are read back as zeros and which are read back

as ones. The number of zeros read back indicates the

amount of memory or I/O space a particular S5320

Pass-Thru region is requesting.

Memory or I/O mapping. If this bit is clear, the

region should be memory mapped. If this bit is

set, the region should be I/O mapped.

D2:1

Location of a memory region. These bits

request that the region be mapped in a particu-

lar part of memory. These bit definitions are

only used for memory mapped regions.

Location

Anywhere in 32-bit memory

space

Below 1 Mbyte in memory space

(Real Mode address space)

Anywhere in 64-bit memory

space (not valid for the S5320)

Reserved

Prefetchable. For memory mapped regions,

the region can be defined as cacheable. If set,

the region is cacheable. If this bit is clear, the

region is not.

D31:30

Pass-Thru region bus width. These two bits are

used by the S5320 to define the data bus width

for a Pass-Thru region. Regardless of the pro-

gramming of other bits in the BADR register, if

D31:30 are zeros, the Pass-Thru region is dis-

abled.

D31

D30

Add-On Bus Width

Region disabled

8 bits

16 bits

32 bits

NV Memory Contents

Pass-Thru Region Definition

54h = BFFFF002h

Pass-Thru region 1 is a 4 Kbyte

region, mapped below 1 Mbyte

in memory space with a 16-bit

Add-On data bus. This memory

region is not cacheable.

58h = 3xxxxxxxh

Pass-Thru region 2 is disabled.

(D31:30 = 00.)

5Ch = FFFFFF81h

Pass-Thru region 3 is a 32-bit,

128 byte I/O-mapped region.

60h = 00000000h

Pass-Thru region 4 is disabled.

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]

DXFR#

DQ[7:0]

PTWAIT#

PTADDR Byte0

PTADR#

Byte1

Byte2

Byte3

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