AND8001/D

http://onsemi.com

2

Using the technique, we add a gate on the clock to get

differential Clock and Clock bar, a flip flop that triggers on

the Clock Bar rising edge (Clock Neg.) to shift the output of

”B” by 90 degrees and a gate to AND/OR two FF output to

produce the 50% output. We get Figure 2, a Divide By 3 that

clocks synchronously with 50% output duty cycle.

Figure 2.

Q

Q

D

C

Q

Q

D

C

Divide By 3 W/50% out

Q

Q

D

C

50% Out

Clk in

ABC

Clk

AQ

BQ

CQ

OUT

The Max frequency of the configuration (figure 2) is

calculated as Clock input freq./2 = Tpd of FF ”B” + Setup

of ”C” + Hold of ”C”.

Example:

Tpd = 1Ns, Setup = !NS and Hold time = 0Ns.

with these numbers the Max Frequency the configuration

can expect is; Cycle time = 2*(1 + 1)Ns or 4 Ns that converts

to 250MHZ.

The Method is usable on other divide by ”N” counters as

well by using the same methodology. The use of different

types of Flip Flops (J,K, S,R, Toggle, ETC.) may produce

fewer components. The type logic used may also dictate

configuration. The configuration should always be checked

for lockup conditions before the design is committed to a

production.

Example:

A Divide By 3 design has all possible states shown in chart

1 but uses only the states shown in chart 2 leaving the states

2,3,4,5, & 7 for possible lockup.

ABC

0000

1100

2010

3110

4001

5101

6011

7111

Chart 1

Chart 2

ABC

0000

1100

6011