AND8066 datasheet(3/8 Pages) ONSEMI

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AND8066/D

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Depending on system requirements, VBB may be

generated by a dedicated supply, a “16” type buffer, or by

using a bypassed resistor voltage divider.

Dedicated Single–Ended Input Structure

A device may have a dedicated single–ended input, having

only one of the internal differential base inputs pinned out of the

package, available to be driven by a signal. Internal circuitry

connects a VBB voltage reference to the other internal,

non–driven input base node of the differential buffer gate, as

shown in Figure 2. This internal, fixed reference voltage, VBB,

is maintained at the midpoint between VIL and VIH for

dedicated single–ended inputs. The internal VBB is derived from

referencing the VCC supply and tracks changes 1:1 in this

supply. Noise and drift in VCC will inject jitter and phase noise

directly into the signal.

DIFFERENTIAL INTERFACE

A standard differential interconnect driver signal will be

received as signal swing. Historically, standard ECL driver

signal swing may range from 750 mV to 1040 mV depending

on the family, although 800 mV is typical. Newer devices may

offer RSECL (Reduced Swing ECL) or Variable Output Swing

(NBSG16VS). Receiver sensitivity is specified by data sheets as

the input swing voltage peak–to–peak (Vpp). Proper output

operation is displayed as the typical amplitude through the entire

range of input swing, from minimum to maximum as shown in

Figure 9: Vpp – Input Swing Voltage Peak–to–Peak. Input

swings greater than specification limit maximum may cause

degraded frequency performance and increased tpd input. Input

swings less than specification minimum will cause diminished

output amplitude due to the device voltage gain and low enough

input amplitude will result in a loss of output signal. All

waveforms are measured with single ended probes with

reference to ground (not as a differential probe value). Operation

in the small signal level range less than Vpp minimum display

a characteristic gain and may obviously be operated as a limited

linear amplifier this input swing range.

Figure 9. Vpp – Input Swing Voltage Peak–to–Peak

Input Vpp

Output Vpp

Max

Min

Typ

Noise common to both differential lines and within the input

operating range will be rejected and ignored by the receiver.

The transfer threshold point is determined by the crosspoint of

the differential signal. A voltage shift in input operating range

of the transfer point has no voltage or timing effect on the

signal, therefore, preserving integrity. A receiver’s tolerance of

common mode interference is illustrated in Figure 10.

Figure 10. Differential Input High Noise Immunity

Input

Output

VIHCMR

Each input signal to a differential pair receiver will display a

Vin HIGH voltage (VIH) level and a Vin LOW voltage VIL.

Proper operation is achieved when the Vin HIGH voltage (VIH)

level falls within spec limits, VIHCMR (Voltage Input High

Common Mode Range) minimum to maximum as represented

in Figure 11.

Figure 11. VIH Common Mode Range, VIHCMR

VIN(pp)

VIH(max)

VIH(min)

VIHCMR

Input

VOUT(pp)

Output

Considerations for Single–Ended and Differential

Interconnects

Several advantages and disadvantages are listed below.

Single–Ended (SE) Interconnects

Advantages may include:

• Decreased board real estate routing.

• Reduced system power demand.

Disadvantages may include:

• Higher jitter, phase error, and duty cycle skew.

• High noise sensitivity.

• Critically narrow interface windows.

• Poor receiver sensitivity.

• Higher EMI emission.

Differential Interconnects

Advantages may include:

• High common mode noise rejection (low noise

sensitivity).

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