AD7763 datasheet(5/32 Pages) AD

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AD7763

Rev. 0 | Page 5 of 32

TIMING SPECIFICATIONS

AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.

Table 3.

Parameter

Limit at TMIN, TMAX

Unit

Description

fMCLK

MHz min

Applied master clock frequency

MHz max

fICLK

500

kHz min

Internal modulator clock derived from MCLK

MHz max

t11

1 × tICLK or 0.5 × tICLK2

typ

SCO high period

t21

1 × tICLK or 0.5 × tICLK

typ

SCO low period

tSCO3

typ

DRDY low period

t3A4

ns typ

SCO rising edge to DRDY falling edge

t3B4

ns typ

SCO rising edge to DRDY rising edge

t45

32 × tSCO3

typ

FSO low period

t4A4, 5

ns typ

SCO rising edge to FSO falling edge

t4B4, 5

ns typ

SCO falling edge to FSO rising edge

6.5

ns max

Initial data access time

t64

ns max

SCO rising edge to SDO valid

0.5 × tSCO3

ns min

SDO valid after SCO falling edge

16 × tSCO3

typ

DRDY rising edge to SDL falling edge

tSCO3

typ

SDL pulse width

t10

5.5

ns max

SDO three-state to SCO rising edge

t11

1 × tSCO3

min

FSI low period

t12

ns min

SDI setup time

t13

ns min

SDI hold time

t14

ns min

FSI setup time

t15

16 × tSCO3

typ

SDL falling edge to SDL falling edge

1 tICLK = 1/fICLK.

2 SCO frequency selected by SCR and CDIV pins.

3 tSCO = t1 + t2.

4 All edges mentioned refer to SCP = 0. Invert SCO edges for SCP = 1.

5 In decimate × 32 mode, this time specification applies only when CDIV = 0 and SCR =1. For all other combinations of CDIV and SCR in decimate × 32 mode, the FSO

signal is constantly logic low.

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