9FG830 datasheet(15/20 Pages) RENESAS

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IDT®

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

1680E—04/04/17

9FG830

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type0

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: Reserved Register

Pin #

Name

Control Function

Type0

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: M/N Programming Enable

Pin #

Name

Control Function

Type0

Default

Bit 7

M/N_EN

PLL M/N Programming

Enable

Disable

Enable

Bit 6

OE_Polarity

Select Polarity of OE

inputs

OE#

Bit 5

REFOUT_En

Enables/Disables REF

Disable

Enable

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBus Table: PLL Frequency Control Register

Pin #

Name

Control Function

Type0

Default

Bit 7

PLL N Div8

N Divider Prog bit 8

Bit 6

PLL N Div9

N Divider Prog bit 9

Bit 5

PLL M Div5

Bit 4

PLL M Div4

Bit 3

PLL M Div3

Bit 2

PLL M Div2

Bit 1

PLL M Div1

Bit 0

PLL M Div0

Byte 10

The decimal

representation of M and

N Divider in Byte 11 and

12 will configure the PLL

VCO frequency.

Default at power up =

latch-in or Byte 0 Rom

table. VCO Frequency

= fXTAL x [NDiv(9:0)+8]

/ [MDiv(5:0)+2]

M Divider Programming

bit (5:0)

Reserved

Byte 9

Reserved

Byte 7

Reserved

Byte 8

Reserved

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