VITESSE

SEMICONDUCTOR CORPORATION

2.488 Gb/s Quad

Data Re-timer

Target Specification

VSC8124

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

2/23/00

G52271-0, Rev. 1.14

Figure 2: Re-timed Serial Output Data Eye Diagram

Table 2: Serial Output Data Specification

NOTES: 1) Jitter generation is measured at worst case power supply and temperature using 155.52 MHz clean reference clock

and clean serial data.

2) Jitter generation and rise, fall time specifications do not apply in re-timer bypass mode.

Parameter

Description

Min

Typ

Max

Units

Conditions

Jitter generation

-

-

12ps rms

Normal Operation

Jitter generation

-

-

15 ps rms

Fast Lock Mode

Jitter generation

-

-

14ps rms

Within 40

µs after

REFCK phase

change

Rise time, fall time

-

-

140

ps

20 to 80%

Period

80%

20%

,