MPC821 datasheet(188/242 Pages) NXP

188 / 242 page

Functional Description

MPC860TFADS Daughter Board Design Specification—Rev 0.1

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

and by MPC860T internal sources.

When Soft reset is generated to the MPC860T, Soft Reset configuration is made available to the MPC

by logic residing over the motherboard. See 4•1•6•3 "Soft Reset Configuration" on page 29 on

MPC8XXFADS User’s Manual.

4•2

Interrupts

Two external interrupts are applied to the MPC via its interrupt controller the ABORT (NMI), which is

generated by a push-button & logic residing over the motherboard, and the other on is the IRQ2 which

is the interrupt of the LXT970 Fast Ethernet Tranceiver.

4•3

Clock Generator

Although most of clock generator logic is found on this board, it is documented within the motherboard

User’s Manual, since, it is common to all daughter boards. See 4•3 "Clock Generator" on page 30 of

the MPC8XXFADS User’s Manual.

4•4

Fast Ethernet Support

The 860TDB has on-board full support for 802.3 Media Independent Interface (MII), made by the

Level One LXT970 device, the connection between the LXT970 and the line can be made by twisted

pair RJ45 connector or by fiber optic connector which is an optional only.

The LXT970 used in the 860TDB has the following features: it is a IEEE 802.3 Compatible which is

a 10BASE-T and 100BASE-TX using a single RJ45 connector. It support an auto-negotiation via Fast

Link Pulse (FLP) exchange and parallel detection for legacy 10BASE-T and 100BASE-TX systems.

MII interface, 100BASE-FX fiber optic capable, configurable through the MII serial port, it can be DTE

repeater or switch application.

The LXT970 has several control pins that can configure the mode of operation these pins are sepa-

rated to two pins groups the WH control pins and the SW control pins, the HW control pins are the

MF(0:4) connected to the DS1, the SW control pins are the TRSTE, FDE and CFG(0:1) which are

controlled via the BCSR4 register.

The following tables illustrate the LXT970 configuration options.

The following table describe the SW control pins controlled via the BCSR4 register which is on the

mother board

TABLE 4-1. MF0 - MF4 Function Description Pins

PIN NAME

FUNCTION

DS1 ON

CONDITION

DS1 OFF

CONDITION

Default

MF0

Auto-negotiation

Disable

Enable

MF1

Repiter/DTE mode

DTE

Repeater

DTE

MF2

Nibble 4B/Symbol 5B

Nibble 4B

Symbol 5B

Nibble 4B

MF3

Scrambler Operation

Enable

Disable

Enable

MF4

Select TX or FX

100TX

100FX

100TX

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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