A43L1632 datasheet(11/43 Pages) AMICC

11 / 43 page

A43L1632

PRELIMINARY

(December, 2004, Version 0.0)

AMIC Technology, Corp.

Simplified Truth Table

Command

CKEn-1 CKEn

RAS CAS

DQM BS0

BS1

A10

/AP

A9~A0,

Notes

Mode Register Set

OP CODE

1,2

Auto Refresh

Entry

Refresh

Self

Refresh

Exit

Bank Active & Row Addr.

Row Addr.

Auto Precharge Disable

Read &

Column Addr. Auto Precharge Enable

Column

Addr.

4,5

Auto Precharge Disable

Write &

Column Addr. Auto Precharge Enable

Column

Addr.

4,5

Burst Stop

Bank Selection

Precharge

Both Banks

Entry

Clock Suspend or

Active Power Down

Exit

Entry

Precharge Power Down Mode

Exit

DQM

No Operation Command

Deep Power Down Entry

Deep Power Down Exit

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note :

1. OP Code: Operand Code

A0~A10, BS0, BS1: Program keys. (@MRS)

2. MRS can be issued only when all banks are at precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions is same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by “Auto”.

Auto/Self refresh can be issued only when all banks are at precharge state.

4. BS0, BS1 : Bank select address.

If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.

If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.

If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.

If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.

If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command cannot be issued.

Another bank read/write command can be issued at every burst length.

6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)

but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

7. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.

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