CY2PD817
Document #: 38-07574 Rev. **
Page 2 of 6
Pin Description[1]
Pin
Name
I/O
Type
Description
2
PCLKI
I, PD
LVPECL
LVPECL reference clock input
3
PCLKI
I, PU/PD
LVPECL
LVPECL reference clock input
6
PCLKO
O
LVPECL
LVPECL clock output
7
PCLKO
O
LVPECL
LVPECL clock output
23, 22
QA[1,0]
O
LVCMOS
Bank A, LVCMOS clock outputs
14, 15, 18, 19
QB[3:0]
O
LVCMOS
Bank B, LVCMOS clock outputs
12
CLRDIV
I, PD
LVCMOS
Clear divider input. See functional Table 1
9
OE
I, PD
LVCMOS
Output enable/disable input. See functional
Table 1
1, 5, 10, 16, 20, 24
VDD
Supply
VDD
2.5V power supply[2]
4, 8, 11, 13, 17, 21
VSS
Supply
Ground
Common ground
Table 1. Functional Table
Control
Default
0
1
CLRDIV
0
Bank A = ÷4, Bank B = ÷2
Bank A = ÷1, Bank B = ÷1
OE
0
All outputs are enabled
All outputs are three-stated
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VDD
DC Supply Voltage
–0.5
3.3
V
VDD
DC Operating Voltage
Functional
2.375
2.625
V
VIN
DC Input Voltage
Relative to VSS, with or VDD
applied
–0.5
VDD + 0.5
V
VOUT
DC Output Voltage
Relative to VSS
–0.5
VDD + 0.5
V
VTT
Output termination Voltage
LVCMOS outputs
VDD / 2
V
LVPECL output
VDD – 2
LU
Latch Up Immunity
Functional
200
–
mA
RPS
Power Supply Ripple
Ripple Frequency < 100 kHz
–
150
mVp-p
TS
Temperature, Storage
Non-functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
0
+85
°C
TJ
Temperature, Junction
Functional
–
+150
°C
ØJC
Dissipation, Junction to Case
Functional
–
42
°C/W
ØJA
Dissipation, Junction to Ambient
Functional
–
105
°C/W
ESDH
ESD Protection (Human Body
Model)
2000
–
V
FIT
Failure in Time
Manufacturing test
10
ppm
Notes:
1.
PU = Internal pull up, PD = Internal pull down.
2.
A 0.1-uF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the trace.
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