TMS320C82 datasheet(2/147 Pages) TI

2 / 147 page

TMS320C82

DIGITAL SIGNAL PROCESSOR

SPRS048 — APRIL 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251-1443

architecture

PP1

(DSP)

PP0

(DSP)

C/D

OCR

FPU

TAP

Crossbar

Figure 1. ‘C82 Block Diagram Showing Datapaths

The ‘C82 Block Diagram shows the major components of the ‘C82: the Master Processor (MP), Parallel

Processors (PPs), Transfer Controller (TC), and JTAG Emulation Interface.

Shared access to on-chip

RAMs is achieved through the Crossbar. Crossbar connections are represented by

. Each PP can

perform three accesses per cycle through its Local, Global, and Instruction ports. The MP can access two

RAMs per cycle through its Crossbar/Data and Instruction ports and the TC can access one RAM through

its crossbar interface. Thus, up to nine simultaneous accesses are supported in each cycle. Addresses can

be changed every cycle, allowing the crossbar matrix to be changed on a cycle-by-cycle basis. Contention

between processors for the same RAM in the same cycle is resolved by a round-robin priority scheme. In

addition to the Crossbar, a 32-bit data path exists between the MP and the TC. This allows the MP to

access TC control registers which are memory-mapped into the MP's memory space.

TMS320C82 Datasheet(PDF) 2 Page - Texas Instruments