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UT54ACTS109 Datasheet(PDF) 1 Page - Aeroflex Circuit Technology

Part # UT54ACTS109
Description  Radiation-Hardened Dual J-K Flip-Flops
PDF  6 Pages
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Manufacturer  AEROFLEX [Aeroflex Circuit Technology]
Direct Link  http://www.aeroflex.com
Logo AEROFLEX - Aeroflex Circuit Technology

UT54ACTS109 Datasheet(HTML) 1 Page - Aeroflex Circuit Technology

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61
RadHard MSI Logic
UT54ACS109/UT54ACTS109
Radiation-Hardened
Dual J-K Flip-Flops
FEATURES
•
radiation-hardened CMOS
- Latchup immune
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K posi-
tive triggered flip-flops. A low level at the preset or clear inputs
sets or resets the outputs regardless of the other input levels.
When preset and clear are inactive (high), data at the J and K
input meeting the setup time requirements are transferred to the
outputs on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
Note:
1. The output levels in this configuration are not guaranteed to meet the mini-
mum levels for VOH if the lows at preset and clear are near VIL maximum. In
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpack
Top View
LOGIC SYMBOL
INPUTS
OUTPUT
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H 1
H 1
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
No Change
H
H
H
H
H
L
H
H
L
X
X
No Change
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR1
J
K1
CLK1
PRE1
Q1
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
8
9
VSS
Q2
Q1
1
2
3
4
5
7
6
16
15
14
13
12
10
11
CLR1
J1
K1
CLK1
PRE1
Q1
VSS
Q1
8
9
VDD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
Q1
(6)
(7)
Q1
Q2
(10)
(9)
Q2
(5)
PRE1
(4)
CLK1
(1)
CLR1
(11)
PRE2
(14)
J2
(12)
CLK2
(13)
K2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
S
C1
R
(2)
J1
J1
(3)
K1
K1
(15)
CLR2


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