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ICS1893AF Datasheet(PDF) 128 Page - Renesas Technology Corp |
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ICS1893AF Datasheet(HTML) 128 Page - Renesas Technology Corp |
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128 / 137 page ![]() ICS1893AF, Rev D 10/26/04 October, 2004 128 Chapter 10 DC and AC Operating Conditions ICS1893AF Data Sheet - Release Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 10.5.15 Reset: Power-On Reset Table 10-22 lists the significant time periods for the power-on reset. The time periods consist of timings of signals on the following pins: • VDD • TXCLK Figure 10-16 shows the timing diagram for the time periods. Figure 10-16. Power-On Reset Timing Diagram Table 10-22. Power-On Reset Timing Time Period Parameter Conditions Min. Typ. Max. Units t1 VDD ≥ 2.7 V to Reset Complete – 40 45 500 ms TXCLK Valid VDD 2.7 V t1 |
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