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ICS1893AF Datasheet(PDF) 124 Page - Renesas Technology Corp |
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ICS1893AF Datasheet(HTML) 124 Page - Renesas Technology Corp |
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124 / 137 page  ICS1893AF, Rev D 10/26/04 October, 2004 124 Chapter 10 DC and AC Operating Conditions ICS1893AF Data Sheet - Release Copyright © 2004, Integrated Circuit Systems, Inc. All rights reserved. 10.5.11 100M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission) Table 10-18 lists the significant time periods for the 100M MII carrier assertion/de-assertion during half-duplex transmission. The time periods consist of timings of signals on the following pins: • TXEN • TXCLK • CRS Figure 10-12 shows the timing diagram for the time periods. Figure 10-12. 100M MII Carrier Assertion/De-Assertion Timing Diagram (Half-Duplex Transmission Only) Table 10-18. 100M MII Carrier Assertion/De-Assertion (Half-Duplex Transmission Only) Time Period Parameter Condi- tions Min. Typ. Max. Units t1 TXEN Sampled Asserted to CRS Assert 0 3 4 Bit times t2 TXEN De-Asserted to CRS De-Asserted 0 3 4 Bit times t2 t1 TXEN TXCLK CRS |
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