HY29F400A datasheet(2/40 Pages) HYNIX

2 / 40 page

Rev. 1.0/Jan. 02

HY29F400A

available.

To eliminate bus contention, the

HY29F400A has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device is compatible with the JEDEC single

power-supply Flash command set standard. Com-

mands are written to the command register using

standard microprocessor write timings, from where

they are routed to an internal state-machine that

controls the erase and programming circuits. De-

vice programming is performed a byte or word at

a time by executing the four-cycle Program com-

mand. This initiates an internal algorithm that au-

tomatically times the program pulse widths and

verifies proper cell margin.

The HY29F400A’s sector erase architecture allows

any number of array sectors to be erased and re-

programmed without affecting the data contents

of other sectors. Device erasure is initiated by ex-

ecuting the Erase command. This initiates an in-

ternal algorithm that automatically preprograms the

array (if it is not already programmed) before ex-

ecuting the erase operation. During erase cycles,

the device automatically times the erase pulse

widths and verifies proper cell margin.

To protect data in the device from accidental or

unauthorized attempts to program or erase the

device while it is in the system (e.g., by a virus),

the device has a Sector Protect function which

hardware write protects selected sectors. The

sector protect and unprotect features can be en-

abled in a PROM programmer. Temporary Sector

Unprotect, which requires a high voltage, allows

in-system erasure and code changes in previously

protected sectors.

Erase Suspend enables the user to put erase on

hold for any period of time to read data from, or

program data to, any sector that is not selected

for erasure. True background erase can thus be

achieved. The device is fully erased when shipped

from the factory.

Addresses and data needed for the programming

and erase operations are internally latched during

write cycles, and the host system can detect

completion of a program or erase operation by

observing the RY/BY# pin, or by reading the DQ[7]

(Data# Polling) and DQ[6] (Toggle) status bits.

Reading data from the device is similar to reading

from SRAM or EPROM devices. Hardware data

protection measures include a low V

CC detector

that automatically inhibits write operations during

power transitions.

The host can place the device into the standby

mode. Power consumption is greatly reduced in

this mode.

BLOCK DIAGRAM

STATE

CONTROL

WE#

CE#

OE#

BYTE#

COMMAND

DQ[15:0]

A[17:0], A-1

CC DETECTOR

TIMER

ERASE VOLTAGE

GENERATOR AND

SECTOR SWITCHES

PROGRAM

VOLTAGE

GENERATOR

X-DECODER

Y-DECODER

4 Mb FLASH

MEMORY

ARRAY

Y-GATING

DATA LATCH

I/O BUFFERS

I/O CONTROL

RESET#

DQ[15:0]

A[17:0], A-1

RY/BY#

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