Table 6. TRGnSPI in Half-Bridge Parallel Mode

TRGnSPIy

TRGnSPIx

CONTROL MODE

0

0

Channels controlled by SPI (both ONCHx and ONCHy set logic high)

0

1

Channels controlled by TRIGA

1

0

Channels controlled by TRIGB

1

1

Channels controlled by SPI (both ONCHx and ONCHy set logic high)

Full-Bridge Configuration

It is possible to configure the half-bridges pairs 0–1, 2–3, 4–5, and 6–7 to make full-bridges and drive latched (bistable)

solenoid valves or even brushed-bipolar DC motors. One pair x–y is declared as a full-bridge by setting bits CMxy_[1:0]

= 10 in the Status Register (refer to the Register Map)

When in Full-Bridge mode, the full-bridge operates in 4 different statuses depending on the content of bits ONCHy and

ONCHx in the Status Register as described in Table 7:

Table 7. Full-Bridge Configuration

(x,y) = (0,1), (2,3), (4,5), (6,7)

ONCHy

ONCHx

OUTx

OUTy

DESCRIPTION

0

0

Hi Z

Hi Z

Hi Z

0

1

VM

VDR/CDR

Y settings

Forward

1

0

VDR/CDR

X settings

VM

Reverse

1

1

GND

GND

Brake

In Table 7, the setting parameters for the control are taken from the configuration register of Channel Y in Forward mode

and from the configuration register of Channel X in Reverse mode. For instance, considering the pair 0–1 in Full-Bridge

mode, when [ONCHy, ONCHx] = [0,1] (forward), the control parameters depend on the content of the Configuration

Register of Channel Y. Vice versa, when [ONCHy, ONCHx] = [1,0] (reverse), then the control depends on the content

of the Configuration Register of Channel X. In this way, it is possible to use different currents levels or timings for latch/

unlatch operations of a latched valve. Notice that the HSnLS bit is ignored for full-bridge operations.

Finally, in Full Bridge Operations, the TRGnSPI bits in the Configuration register enables/disable the drivers as shown in

Table 8:

Table 8. TRGnSPI in Full-Bridge Mode

TRGnSPIy

TRGnSPIx

CONTROL MODE

0

0

Channels controlled by SPI

0

1

Channels controlled by SPI

1

0

Channels controlled by SPI

1

1

Channels controlled by TRIGA/TRIGB

Protection Circuits

The MAX22200 features a full set of protections including undervoltage (UVLO), overcurrent (OCP), and

overtemperature (OVT). The device also features diagnostic functions such as open-load detection (OL), detection of

plunger movement (DPM), "hit current not reached" detection (HHF), and communication error detection (COMF). An

open-drain fault indication pin (FAULT) is provided to signal detected faults out to the controller. Each of the above

mentioned failures (with the exception of the COMF) are by default signaled out to the FAULT pin. Fault indication can

be masked by setting high the corresponding bits into the Status registers (STATUS[15:8]). When a Fault is masked, a

Fault event does not activate the FAULT pin.

MAX22200

36V, 1A Octal Integrated Serial-Controlled

Solenoid and Motor Driver

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