21 / 41 page
Data Sheet
INDT/R165B
INDT/R330B
Date: 2005-02-18 Revision: 1.1
Page 21 of 41
(b) Receiver pixel interface
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t5/6
t7
Figure 3.6: Pixel Interface Timing Diagram At Rising Edge At Rx
Parameter
Description
Min.
Typ.
Max.
Unit
t5
Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA)
1.8
4.0
4.4
ns
t6
Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA)
1.6
3.0
4.2
ns
t7
Pixel data and ctrl signal hold time to pixel clock at Rx
0.5
1.2
1.4
ns
Table 3.12: Pixel Interface Timing Table At Rising Edge At Rx
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t8/9
t10
Figure 3.7: Pixel Interface Timing Diagram At Falling Edge At Rx
Parameter
Description
Min.
Typ.
Max.
Unit
t8
Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA)
2.2
3.8
4.7
ns
t9
Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA)
1.0
2.9
3.7
ns
t10
Pixel data and ctrl signal hold time to pixel clock at Rx
0.5
1.2
1.3
ns
Table 3.13: Pixel Interface Timing Table At Falling Edge At Rx
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