ADF4108 datasheet(18/20 Pages) AD

18 / 20 page

ADF4108

Rev. 0 | Page 18 of 20

INTERFACING

The ADF4108 has a simple SPI™-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When LE (Latch Enable) goes high, the 24 bits that

have been clocked into the input register on each rising edge of

CLK are transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device is

833 kHz or one update every 1.2 μs. This is certainly more than

adequate for systems that have typical lock times in hundreds of

microseconds.

ADuC812 INTERFACE

Figure 21 shows the interface between the ADF4108 and the

ADuC812 MicroConverter®. Since the ADuC812 is based on an

8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4108 needs a

24-bit word. This is accomplished by writing three 8-bit bytes

from the MicroConverter to the device. When the third byte

has been written, the LE input should be brought high to

complete the transfer.

On first applying power to the ADF4108, it needs four writes

(one each to the initialization latch, function latch, R counter

latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and to detect lock (MUXOUT configured as

lock detect and polled by the port input).

When operating in the mode described, the maximum

SCLOCK rate of the ADuC812 is 4 MHz. This means that the

maximum rate at which the output frequency can be changed

will be 166 kHz.

CLK

DATA

MUXOUT

(LOCK DETECT)

MOSI

ADF4108

SCLOCK

I/O PORTS

ADuC812

Figure 21. ADuC812 to ADF4108 Interface

ADSP-2181 INTERFACE

Figure 22 shows the interface between the ADF4108 and the

ADSP-21xx Digital Signal Processor. The ADF4108 needs a

24-bit serial word for each latch write. The easiest way to

accomplish this using the ADSP21xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated. Set up the word

length for 8 bits and use three memory locations for each 24-bit

word. To program each 24-bit latch, store the three 8-bit bytes,

enable the autobuffered mode, and then write to the transmit

transfer.

CLK

DATA

MUXOUT

(LOCK DETECT)

MOSI

ADF4108

SCLOCK

I/O FLAGS

ADSP-21xx

TFS

Figure 22. ADSP-21xx to ADF4108 Interface

ADF4108 Datasheet(PDF) 18 Page - Analog Devices

ADF4108 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL