Integrated

Circuit

Systems, Inc.

ICS9250-50

0594B—09/14/05

Block Diagram

Pin Configuration

Recommended Application:

815B Solano B step style chipset

Output Features:

•

2 - CPUs @ 2.5V, up to 133MHz.

•

13 - SDRAM @ 3.3V, up to 133MHz.

•

3 - 3V66 @ 3.3V, 2x PCI MHz.

•

8 - PCI @ 3.3V

•

1 - 48MHz, @ 3.3V fixed

•

1 - 24/48MHz @ 3.3V

•

1 - REF @ 3.3V, 14.318MHz.

•

1 - IOAPIC @ 2.5V 16.67MHz.

Features:

•

Support PC133 SDRAM.

•

Up to 133MHz frequency support

•

Support power management through PD#

•

Spread spectrum for EMI control

(± 0.25% Center Spread or 0 to -0.5% down spread)

•

Uses external 14.318MHz crystal

•

FS pins for frequency select

Key Specifications:

•

CPU Output Jitter: <250ps

•

CPU Output Skew: <175ps

•

PCI Output Skew: <500ps

•

3V66 Output Skew <175ps

•

For group skew timing, please refer to the

Group Timing Relationship Table.

Frequency Generator & Integrated Buffers for PIII & Tualatin™

56-Pin 300 mil SSOP

1. These pins will have 1.5 to 2X drive strength.

* 120K ohm pull-up to VDD on indicated inputs.

Functionality

For other hardware/I

2C selectable frequencies please

refer to Byte 0 frequency select register.

VDDA

X1

X2

GNDA

GND3V66

3V66-1

3V66-2

VDD3V66

VDDPCI

*FS0/PCICLK0

*FS1/PCICLK1

*SEL24_48#/PCICLK2

GNDPCI

PCICLK3

PCICLK4

PCICLK5

VDDPCI

PCICLK6

PCICLK7

GNDPCI

Vtt_PWRGD/PD#

SCLK

SDATA

VDDSDR

SDRAM11

SDRAM10

GNDSDR

3V66-0

1

1

1

REF0/FS4*

VDDLAPIC

IOAPIC

VDDLCPU

CPUCLK0

CPUCLK1

GNDLCPU

GNDSDR

SDRAM0

SDRAM1

SDRAM2

VDDSDR

SDRAM3

SDRAM4

SDRAM5

GNDSDR

SDRAM6

SDRAM7

SDRAM_F

VDDSDR

GND48

24_48MHz/FS2 *

48MHz/FS3*

VDD48

VDDSDR

SDRAM8

SDRAM9

GNDSDR

1

1

1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK (1:0)

2

12

8

3

SDRAM (11:0)

IOAPIC

PCICLK (7:0)

SDRAM_F

3V66 (2:0)

X1

X2

XTAL

OSC

CPU

DIVDER

SDRAM

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

FS(4:0)

PD#

Vtt_PWRGD

SEL24_48#

SDATA

SCLK

Control

Logic

Config.

Reg.

/ 2

REF0

FS4 FS3 FS2 FS1 FS0

CPU

SDRAM

3V66

PCI

0

0000

66.67

100.00

66.67

33.33

0

1000

100.00

100.00

66.67

33.33

1

0000

133.33

133.33

66.67

33.33

1

1000

133.33

100.00

66.67

33.33

Power Groups

VDD48 = Fixed PLL power

GND48 = Fixed PLL GND

VDDA = Power for CPU PLL

GNDA = GND for CPU PLL